Testing redundant asynchronous circuits by variable phase splitting

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Testing redundant asynchronous circuits by variable phase splitting

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European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents

Grenoble, France

Pages: 328 - 333

Year of Publication: 1994

ISBN:0-89791-685-9

Authors

Luciano Lavagno	Dip. di Elettronica, Politecnico di Torino, 10129 Torino, Italy
Antonio Lioy	Dip. di Informatica, Politecnico di Torino, 10129 Torino, Italy
Michael Kishinevsky	Dept. of Computer Science, Technical University of Denmark, DK-2800 Lyngby, Denmark

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 2, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	2	Robert King Brayton , Alberto L. Sangiovanni-Vincentelli , Curtis T. McMullen , Gary D. Hachtel, Logic Minimization Algorithms for VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1984
	3	M. J. Bryan. S. Devadas. and K. Keutzer. Testability- Preserving Circuit Transformations. In Proceedings of the International Conference on Computer-Aided Design, November 1990.
	4	S. Devadas and K. Keutzer. Synthesis of robust delay-fault testable circuits: Theory. IEEE Transacfions on Computer- Aided Design, 11:87-101, January 1992.
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	6	Alex Kondratyev , Michael Kishinevsky , Bill Lin , Peter Vanbekbergen , Alex Yakovlev, Basic gate implementation of speed-independent circuits, Proceedings of the 31st annual conference on Design automation, p.56-62, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196275]
	7	S. Kundu and S. M. Reddy. On the design of robust testable CMOS combinational logic circuits. In Proceedings of the Inrernariontrl ConJberrce on Fault Tolerant Computing SysfCNfS, pages 220-225. I9t18.
	8	L. Lavagno , K. Keutzer , A. Sangiovanni-Vincentelli, Algorithms for synthesis of hazard-free asynchronous circuits, Proceedings of the 28th conference on ACM/IEEE design automation, p.302-308, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127685]
	9	L. Lavagno, K. Keutzer. and A. Sangiovanni-Vincentelli. Synthesis for testability techniques for asynchronous circuits. In Proceedings of the Internarional Conference on Computer-Aided Design, November 1991.
	10	L. Lavagno. M. Kishinevsky, and A.Lioy. Testing redundant asynchronous circuits. Technical Report ID-TR: 1993-124, Technical University of Denmark, October 1993.
	11	Alian J. Martin , Pieter J. Hazewindus, Testing delay-insensitive circuits, Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI, p.118-132, April 1991
	12	Steven M. Nowick , David L. Dill, Exact two-level minimization of hazard-free logic with multiple-input changes, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.626-630, November 1992, Santa Clara, California, United States
	13	Marly Roncken , Ronald Saeijs, Linear Test Times for Delay-Insensitive Circuits: a Compilation Strategy, Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies, p.13-27, March 31-April 02, 1993
	14	Stephen H. Unger, Asynchronous Sequential Switching Circuit, Krieger Publishing Co., Inc., Melbourne, FL, 1983
	15	V. I. Varshavsky, M. A. Kishinevsky, V. B. Madhovsky, V. A. Peschanshy. L. Y. Kosenblum. A. R. Taubin, and B. S. Tzirlin. Self:rit,rrd Corurol of Concurrent Processes. Kluwer Academic publisher, 19YO. (Russian edition: 1986).
	16	Kenneth Y. Yun , David L. Dill, Automatic synthesis of 3D asynchronous state machines, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.576-580, November 1992, Santa Clara, California, United States

CITED BY 3

	Michael Kishinevsky , Alex Kondratyev , Luciano Lavagno , Alexander Saldanha , Alexander Taubin, Partial scan delay fault testing of asynchronous circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.728-735, November 09-13, 1997, San Jose, California, United States
	Oriol Roig , Jordi Cortadella , Marco A. Peña , Enric Pastor, Automatic generation of synchronous test patterns for asynchronous circuits, Proceedings of the 34th annual conference on Design automation, p.620-625, June 09-13, 1997, Anaheim, California, United States
	Luciano Lavagno , Steven M. Nowick, Asynchronous control circuits, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001