A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions

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A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions

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European Design Automation Conference archive
Proceedings of the conference on European design automation table of contents

Grenoble, France

Pages: 271 - 276

Year of Publication: 1994

ISBN:0-89791-685-9

Authors

Roman Kužnar	Department of ECE, Tržaška 25, University of Ljubljana, 61000 Ljubljana, Slovenia
Baldomir Zajc	Department of ECE, Tržaška 25, University of Ljubljana, 61000 Ljubljana, Slovenia
Franc Brglez	CBL, Dept. of Elec. & Computer Eng., North Carolina State University, Raleigh, N.C.

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

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Downloads (6 Weeks): 0, Downloads (12 Months): 3, Citation Count: 5

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Roman Kužnar , Franc Brglez , Krzysztof Kozminski, Cost minimization of partitions into multiple devices, Proceedings of the 30th international conference on Design automation, p.315-320, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164910]
	2	Roman Kužnar , Franc Brglez , Baldomir Zajc, Multi-way netlist partitioning into heterogeneous FPGAs and minimization of total device cost and interconnect, Proceedings of the 31st annual conference on Design automation, p.238-243, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196364]
	3	Nan-Chi Chou , Lung-Tien Liu , Chung-Kuan Cheng , Wei-Jin Dai , Rodney Lindelof, Circuit partitioning for huge logic emulation systems, Proceedings of the 31st annual conference on Design automation, p.244-249, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196365]
	4	Nam Sung Woo , Jaeseok Kim, An efficient method of partitioning circuits for multiple-FPGA implementation., Proceedings of the 30th international conference on Design automation, p.202-207, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164669]
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	7	C. J. Alpert , A. B. Kahng, Geometric embeddings for faster and better multi-way netlist partitioning, Proceedings of the 30th international conference on Design automation, p.743-748, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165115]
	8	Pak K. Chan , Martine D. F. Schlag , Jason Y. Zien, Spectral K-way ratio-cut partitioning and clustering, Proceedings of the 30th international conference on Design automation, p.749-754, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165117]
	9	Jason Cong , M'Lissa Smith, A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design, Proceedings of the 30th international conference on Design automation, p.755-760, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165119]
	10	Minshine Shih , Ernest S. Kuh, Quadratic Boolean programming for performance-driven system partitioning, Proceedings of the 30th international conference on Design automation, p.761-765, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.165121]
	11	C. J. Alpert , A. B. Kahng, Multi-way partitioning via spacefilling curves and dynamic programming, Proceedings of the 31st annual conference on Design automation, p.652-657, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196603]
	12	Bernhard M. Riess , Konrad Doll , Frank M. Johannes, Partitioning very large circuits using analytical placement techniques, Proceedings of the 31st annual conference on Design automation, p.646-651, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196602]
	13	Jason Cong , Zheng Li , Rajive Bagrodia, Acyclic multi-way partitioning of Boolean networks, Proceedings of the 31st annual conference on Design automation, p.670-675, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196609]
	14	R. L. Russo, P. H. Odden, and P. K. Wolff. A heuristic prw cedure for the partitioning and mapping of computer logic graphs. IEEE Transaction on Computers, 20:1455-1462, 1971.
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	16	James Hwang , Abbas El Gamal, Optimal replication for min-cut partitioning, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.432-435, November 1992, Santa Clara, California, United States
	17	S. Dey, F. Brglez, and G. Kedem. Circuit Partitioning for Logic Synthesis. IEEE Journal of Solid-State Circuits, 26(3):350 - 363, March 1991.
	18	Sujit Dey , Franc Brglez , Gershon Kedem, Partitioning Sequential Circuits for Logic Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.70-76, October 14-16, 1991
	19	S. Dey, F. Brglez, and G. Kedem. Identification and Resyntho sis of Pipelines in Se uential Networks. III A. Halaas and P.B. Denyer, editors, VL 2 1'91. @IFIP Elsevier Science Publishers B.V. (North-Holland), 1992.
	20	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	21	F. Brglez, D. Bryan, and K. Kozminski. Combinational Profiles of S uential Benchmark Circuits. In IEEE 1989 Intemationa Symposium on Circuit-s and S stems - ISCAS89, 7 pages 1924-1934, May 1989. Sen d e-mail to benchmarksQcbl.ncsu.edu for autoreply and more details about the directory pub/benchmark/ISCASSQ available with ftp.
	22	R. Kuinar, F. Brglez, and K. Kozminski. Partitioning Digital Circuits for Implementation in Multiple FPGA ICs. Technical Report TR-93-03, MCNC, Research Triangle Park, N.C., March 1993.

CITED BY 5

	Wai-Kei Mak , Evangeline F. Y. Young, Temporal logic replication for dynamically reconfigurable FPGA partitioning, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Helena Krupnova , Gabriele Saucier, Iterative improvement based multi-way netlist partitioning for FPGAs, Proceedings of the conference on Design, automation and test in Europe, p.117-es, January 1999, Munich, Germany
	Joachim Pistorius , Edmée Legai , Michel Minoux, Generation of very large circuits to benchmark the partitioning of FPGA, Proceedings of the 1999 international symposium on Physical design, p.67-73, April 12-14, 1999, Monterey, California, United States
	Roman Kužnar , Franc Brglez, PROP: a recursive paradigm for area-efficient and performance oriented partitioning of large FPGA netlists, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.644-649, November 05-09, 1995, San Jose, California, United States
	Sverre Wichlund, On multilevel circuit partitioning, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.505-511, November 08-12, 1998, San Jose, California, United States