Interface timing verification with application to synthesis

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Interface timing verification with application to synthesis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 106 - 112

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Elizabeth A. Walkup	Department of Computer Science and Engineering, University of Washington, Seattle, WA
Gaetano Borriello	Department of Computer Science and Engineering, University of Washington, Seattle, WA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 5, Citation Count: 11

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Gaetano Borriello, A New Interface Specification Methodology and, University of California at Berkeley, Berkeley, CA, 1988
	2	Anthony Joseph Gahlinger, Coherence and satisfiability of waveform timing specifications, University of Waterloo, Waterloo, Ont., Canada, 1990
	3	Kenneth L. McMillan , David L. Dill, Algorithms for Interface Timing Verification, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.48-51, October 11-14, 1992
	4	Peter Vanbekbergen, Gert Goossens, and Hugo De Man. Specification and analysis of timing constraints in signal transition graphs. In Proceedings of the European Design Automation Conference, March 1992.
	5	Peter Vanbekbergen. Synthesis of Asynchronous Controllers from Graph-Theoretic Specifications. PhD thesis, Katholieke Universiteit Leuven, September 1993.
	6	Bruce Gladstone. Specification of timing in a digital system. ASIC and EDA, pages 46-52, August 1993.
	7	Chris Myers. Synthesis of timed asynchronous circuits. IEEE Transactions on VLSI Systems, June 1993.
	8	Elizabeth A. Walkup and Gaetano Borriello. Interface timing verification with combined max and linear constraints. Technical Report 94-03-04, University of Washington Department of Computer Science, March 1994.

CITED BY 11

	Ki-Seok Chung , Rajesh K. Gupta , Taewhan Kim , C. L. Liu, Synthesis and Optimization of Combinational Interface Circuits, Journal of VLSI Signal Processing Systems, v.31 n.3, p.243-261, July 2002
	Ki-Seok Chung , Rajesh K. Gupta , C. L. Liu, An algorithm for synthesis of system-level interface circuits, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.442-447, November 10-14, 1996, San Jose, California, United States
	Ti-Yen Yen , Wayne Wolf , Al Casavant , Alex Ishii, Efficient algorithms for interface timing verification, Proceedings of the conference on European design automation, p.34-39, September 19-23, 1994, Grenoble, France
	Tod Amon , Gaetano Borriello , Jiwen Liu, Making complex timing relationships readable: Presburger formula simplicication using don't cares, Proceedings of the 35th annual conference on Design automation, p.586-590, June 15-19, 1998, San Francisco, California, United States
	Tod Amon , Gaetano Borriello , Taokuan Hu , Jiwen Liu, Symbolic timing verification of timing diagrams using Presburger formulas, Proceedings of the 34th annual conference on Design automation, p.226-231, June 09-13, 1997, Anaheim, California, United States
	Pierre Girodias , Eduard Cerny, Interface Timing Verification with Delay Correlation Using Constraint Logic Programming, Proceedings of the 1997 European conference on Design and Test, p.12, March 17-20, 1997
	Ti-Yen Yen , Alex Ishii , Al Casavant , Wayne Wolf, Efficient Algorithms for Interface Timing Verification, Formal Methods in System Design, v.12 n.3, p.241-265, April 1, 1998
	Pai H. Chou , Ross B. Ortega , Gaetano Borriello, The Chinook hardware/software co-synthesis system, Proceedings of the 8th international symposium on System synthesis, p.22-27, September 13-15, 1995, Cannes, France
	Uwe Schwiegelshohn , Lothar Thiele, Dynamic Min-Max Problems, Discrete Event Dynamic Systems, v.9 n.2, p.111-134, May 1999
	Philippe Coussy , Emmanuel Casseau , Pierre Bomel , Adel Baganne , Eric Martin, A formal method for hardware IP design and integration under I/O and timing constraints, ACM Transactions on Embedded Computing Systems (TECS), v.5 n.1, p.29-53, February 2006
	Annette Bunker , Ganesh Gopalakrishnan , Sally A. Mckee, Formal hardware specification languages for protocol compliance verification, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.9 n.1, p.1-32, January 2004