Exact minimum cycle times for finite state machines

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Exact minimum cycle times for finite state machines

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 100 - 105

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

William K. C. Lam	Hewlett-Packard Co., Palo Alto, CA
Robert K. Brayton	Department of EECS, University of California, Berkeley
Alberto L. Sangiovanni-Vincentelli	Department of EECS, University of California, Berkeley

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 5, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Pranav Ashar , Sujit Dey , Sharad Malik, Exploiting multi-cycle false paths in the performance optimization of sequential circuits, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.510-517, November 1992, Santa Clara, California, United States
	2	H. C. Chen and D. H. Du. Path sensitization in critical path problem. 1990 ACM Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 1990.
	3	S. Devadas , K. Keutzer , S. Malik , A. Wang, Certified timing verification and the transition delay of a logic circuit, Proceedings of the 29th ACM/IEEE conference on Design automation, p.549-555, June 08-12, 1992, Anaheim, California, United States
	4	S. Devadas, K. Keutzer, and S. Malik. Delay computation in combinational logic circuits: Theory and algorithms. IEEE/ACM International Conference on Computer-AidedDesign, Nov. 1991.
	5	John E. Hopcroft , Jeffrey D. Ullman, Introduction To Automata Theory, Languages, And Computation, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1990
	6	William K. C. Lam , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Circuit delay models and their exact computation using Timed Boolean Functions, Proceedings of the 30th international conference on Design automation, p.128-134, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164625]
	7	W. Lam, R. Brayton, and A. Sangiovanni-Vincentelli. Minimum cycle time of synchronous circuit with bounded delays. UC Berkeley ERL memorandum: UCB/ERL M92/56, May 1992.
	8	Patrick C. McGeer , Robert K. Brayton, Provably correct critical paths, Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI, p.119-142, June 1989, Cambridge, Massachusetts, United States
	9	P. McGeer, A. Saldanha, P. Stephan, R. Brayton, and A. Sangiovanni-Vincentelli. Timing analysis and delay-fault test generation using path recursive functions. IEEE International Conference on Computer-Aided Design, pages 180-183, Nov. 1991.

CITED BY 2

	Z. Hasan , M. J. Ciesielski, Elimination of multi-cycle false paths by state encoding, Proceedings of the 1995 European conference on Design and Test, p.155, March 06-09, 1995
	Suchismita Roy , P. P. Chakrabarti , Pallab Dasgupta, Event propagation for accurate circuit delay calculation using SAT, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.3, p.1-23, August 2007