Resynthesis and retiming for optimum partial scan

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Resynthesis and retiming for optimum partial scan

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 87 - 93

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Srimat T. Chakradhar	C&C Research Laboratories, NEC, 4 Independence Way, Princeton, NJ
Sujit Dey	C&C Research Laboratories, NEC, 4 Independence Way, Princeton, NJ

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 4, Citation Count: 10

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references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
	2	D.H. Lee and S.M. Reddy. On Determining Scan Flip-Flops in Partial-Scan Designs. In Proceedings of the International Conference on Computer-Aided Design, pages 322- 325, November 1990.
	3	V. Chickermane and J. H. Patel. An Optimization Based Approach to the Partial Scan Design Problem. In Proceedings of the International Test Conference, pages 377 - 386, September 1990.
	4	Dimitrios Kagaris , Spyros Tragoudas, Partial scan with retiming, Proceedings of the 30th international conference on Design automation, p.249-254, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164881]
	5	S. Dey and S. T. Chakradhar. Retiming Sequential Circuits To Enhance Testability. In VLSI Test Symposium, April 1994.
	6	C.E. Leiserson and J.B. Saxe. Retiming Synchronous Circuitry. Algorithmica, 6:5 - 35, 1991.
	7	S. T. Chakradhar and S. Dey. Retiming and Resynthesis for Optimum Partial Scan. Technical report, C&C Research Labs, NEC USA, October 1993.
	8	S. Yang. Logic Synthesis and Optimization Benchmarks, User Guide Version 3.0. In International Workshop on Logic Synthesis, MCNC, Research Triangle Park, NC, May 1991.
	9	Srimat T. Chakradhar , Arun Balakrishnan , Vishwani D. Agrawal, An exact algorithm for selecting partial scan flip-flops, Proceedings of the 31st annual conference on Design automation, p.81-86, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196285]

CITED BY 10

	Clay Gloster , Franc Brglez, Partial scan selection for user-specified fault coverage, Proceedings of the conference on European design automation, p.111-116, September 18-22, 1995, Brighton, England
	Xun Liu , Marios C. Papaefthymiou , Eby G. Friedman, Minimizing sensitivity to delay variations in high-performance synchronous circuits, Proceedings of the conference on Design, automation and test in Europe, p.126-es, January 1999, Munich, Germany
	Xun Liu , Marios C. Papaefthymiou , Eby G. Friedman, Maximizing performance by retiming and clock skew scheduling, Proceedings of the 36th ACM/IEEE conference on Design automation, p.231-236, June 21-25, 1999, New Orleans, Louisiana, United States
	Qiushuang Zhang , Ian Harris, Partial BIST insertion to eliminate data correlation, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.395-399, November 07-11, 1999, San Jose, California, United States
	Dimitrios Kagaris , Spyros Tragoudas, Retiming-Based Partial Scan, IEEE Transactions on Computers, v.45 n.1, p.74-87, January 1996
	Huoy-Yu Liou , Ting-Ting Y. Lin, Area efficient pipelined pseudo-exhaustive testing with retiming, Proceedings of the 33rd annual conference on Design automation, p.274-279, June 03-07, 1996, Las Vegas, Nevada, United States
	Peichen Pan , C. L. Liu, Partial scan with pre-selected scan signals, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.189-194, June 12-16, 1995, San Francisco, California, United States
	Dong Xiang , Janak H. Patel, Partial Scan Design Based on Circuit State Information and Functional Analysis, IEEE Transactions on Computers, v.53 n.3, p.276-287, March 2004
	Peichen Pan , C. L. Liu, Partial Scan with Preselected Scan Signals, IEEE Transactions on Computers, v.48 n.9, p.1000-1005, September 1999
	Srimat T. Chakradhar , Arun Balakrishnan , Vishwani D. Agrawal, An exact algorithm for selecting partial scan flip-flops, Proceedings of the 31st annual conference on Design automation, p.81-86, June 06-10, 1994, San Diego, California, United States