Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications

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Implicit computation of minimum-cost feedback-vertex sets for partial scan and other applications

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 77 - 80

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Pranav Ashar	C&C Research Labs, NEC USA, Princeton, NJ
Sharad Malik	Dept. of EE, Princeton Univ., Princeton, NJ

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 9

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	g. Agrawal and K. Cheng. A complete solution to the partial scan problem. In The Proceedings of the International Test Conference, pages 44-51, September 1987.
	2	F. Brglez, D. Bryan, and K. Kozminski. Combinational Profiles of Sequential Benchmark Circuits. In Proceedings of the International Symposium on Circuits and Systems, Portland, Oregon, May 1989.
	3	Srimat T. Chakradhar , Arun Balakrishnan , Vishwani D. Agrawal, An exact algorithm for selecting partial scan flip-flops, Proceedings of the 31st annual conference on Design automation, p.81-86, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196285]
	4	K-T. Cheng and V. D. Agrawal. An economical scan design for sequential logic test generation. In The Proceedings of the Fault Tolerant Comupting Symposium, pages 28-35, June 1989.
	5	Michael R. Garey , David S. Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, W. H. Freeman & Co., New York, NY, 1979
	6	D. Lee and M. Reddy. On determining scan flip-flops in partialscan designs. In Proceedings of the International Conference on Computer-Aided Design, pages 322-325, November 1990.
	7	Errol L. Lloyd , Mary Lou Soffa , Ching-Chy Wang, On locating minimum feedback vertex sets, Journal of Computer and System Sciences, v.37 n.3, p.292-311, Dec. 1988 [doi>10.1016/0022-0000(88)90009-8]
	8	Sungju Park , Sheldon B. Akers, A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination, Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design, p.303-311, September 20-24, 1992
	9	G. Smith and R. Walford. The identification of a minimal feedback vertex set of a directed graph. In IEEE Transactions on Circuits and Systems, volume CAS-22, 1, January 1975.
	10	E. Trischler. Incomplete scan design with an automatic test generation methodology. In The Proceedings of the International Test Conference, pages 153-162, November 1980.

CITED BY 9

	Krishnendu Chakrabarty, A synthesis-for-transparency approach for hierarchical and system-on-a-chip test, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.2, p.167-179, April 2003
	Dong Xiang , Janak H. Patel, Partial Scan Design Based on Circuit State Information and Functional Analysis, IEEE Transactions on Computers, v.53 n.3, p.276-287, March 2004
	Peichen Pan , C. L. Liu, Partial scan with pre-selected scan signals, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.189-194, June 12-16, 1995, San Francisco, California, United States
	Bruce S. Greene , Samiha Mourad, Partial Scan Testing on the Register-Transfer Level, Journal of Electronic Testing: Theory and Applications, v.18 n.6, p.613-626, December 2002
	Peichen Pan , C. L. Liu, Partial Scan with Preselected Scan Signals, IEEE Transactions on Computers, v.48 n.9, p.1000-1005, September 1999
	Toshinobu Ono, Selecting partial scan flip-flops for circuit partitioning, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.646-650, November 06-10, 1994, San Jose, California, United States
	Chih-Chang Lin , Mike Tien-Chien Lee , Malgorzata Marek-Sadowska , Kuang-Chien Chen, Cost-free scan: a low-overhead scan path design methodology, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.528-533, November 05-09, 1995, San Jose, California, United States
	Srimat T. Chakradhar , Arun Balakrishnan , Vishwani D. Agrawal, An exact algorithm for selecting partial scan flip-flops, Proceedings of the 31st annual conference on Design automation, p.81-86, June 06-10, 1994, San Diego, California, United States
	Peter Dahlgren, Oscillation control in logic simulation using dynamic dominance graphs, Proceedings of the 33rd annual conference on Design automation, p.155-160, June 03-07, 1996, Las Vegas, Nevada, United States