A modular partitioning approach for asynchronous circuit synthesis

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A modular partitioning approach for asynchronous circuit synthesis

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 31st annual Design Automation Conference table of contents

San Diego, California, United States

Pages: 63 - 69

Year of Publication: 1994

ISBN:0-89791-653-0

Authors

Ruchir Puri	Dept. of Electrical & Computer Engineering, University of Calgary, Calgary, Canada T2N 1N4
Jun Gu	Dept. of Electrical & Computer Engineering, University of Calgary, Calgary, Canada T2N 1N4

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
EDAC : Electronic Design Automation Consortium

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 0, Downloads (12 Months): 3, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Tam-Anh Chu. Synthesis of Self-Timed VLSI Circuits from Graph-theoretic Specifications. PhD thesis, Dept. of Electrical Engineering and Computer Science, MIT, June 1987.
	2	Jun Gu, Efficient local search for very large-scale satisfiability problems, ACM SIGART Bulletin, v.3 n.1, p.8-12, Jan. 1992 [doi>10.1145/130836.130837]
	3	Jun Gu , Wei Wang, A Novel Discrete Relaxation Architecture, IEEE Transactions on Pattern Analysis and Machine Intelligence, v.14 n.8, p.857-865, August 1992 [doi>10.1109/34.149596]
	4	J. Gu. Local search for satisfiability (SAT) problem. IEEE Trans. on Systems, Man, and Cybernetics, 23(4):1108-1129, Jul./Aug. 1993.
	5	Jun Gu, Constraint-Based Searching: Algorithms and Architectures, Cambridge University Press, New York, NY, 2004
	6	J. Gu, Global Optimization for Satisfiability (SAT) Problem, IEEE Transactions on Knowledge and Data Engineering, v.6 n.3, p.361-381, June 1994 [doi>10.1109/69.334864]
	7	J. Gu. Optimization Algorithms for SatisfiabiIity (SAT) Problem. In New Advances in Optimization and Approximation. Ding-Zhu Du (ed), pages 72-154. Kluwer Academic Publishers, Boston, MA, Jan. 1994.
	8	J. Gu, P.W. Purdom, and B.W. Wah. Algorithms for Satisfiability (SAT) Problem: A Survey. 1993, To appear.
	9	J. Gu and R. Purl. A Preprocessor for Satisfiability Testing: A Case Study in Asynchronous Circuit Synthesis. 1993, To appear.
	10	John E. Hopcroft , Jeffrey D. Ullman, Introduction To Automata Theory, Languages, And Computation, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1990
	11	L. Lavagno. Personal communication, Sept., 1993.
	12	L. Lavagno , K. Keutzer , A. Sangiovanni-Vincentelli, Algorithms for synthesis of hazard-free asynchronous circuits, Proceedings of the 28th conference on ACM/IEEE design automation, p.302-308, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127685]
	13	L. Lavagno , C. W. Moon , R. K. Brayton , A. L. Sangiovanni-Vincentelli, Solving the state assignment problem for signal transition graphs, Proceedings of the 29th ACM/IEEE conference on Design automation, p.568-572, June 08-12, 1992, Anaheim, California, United States
	14	Kuan-Jen Lin , Chen-Shang Lin, Automatic synthesis of asynchronous circuits, Proceedings of the 28th conference on ACM/IEEE design automation, p.296-301, June 17-22, 1991, San Francisco, California, United States [doi>10.1145/127601.127684]
	15	T. Murata. Petri nets: Properties, analysis and applications. Proc. of the IEEE, 77(4):541-580, April 1989.
	16	R. Puri , J. Gu, An efficient algorithm for Microword length minimization, Proceedings of the 29th ACM/IEEE conference on Design automation, p.651-656, June 08-12, 1992, Anaheim, California, United States
	17	R. Purl and J. Gu. An Efficient Algorithm to Search for Minimal Closed Covers in Sequential Machines. IEEE Trans. on CAD, 12(6):737-745, June 1993.
	18	R. Purl and J. Gu. Asynchronous Circuit Synthesis: Persistency and Complete State Coding Constraints in Signal Transition Graphs. International Journal of Electronics, 75(5):933-940, Nov. 1993.
	19	Ruchir Puri , Jun Gu, A divide-and-conquer approach for asynchronous interface synthesis, Proceedings of the 7th international symposium on High-level synthesis, p.118-125, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada
	20	P.R. Stephan, R. K. Brayton, and A. Sangiovanni-Vincentelli. Combinational Test Generation Using Satisfiability. Technical Report ERL M92/112, U.C.Berkeley, Oct., 1992.
	21	P. Vanbekbergen, G. Goossens, F. Catthoor, and H. De Man. Optimized Synthesis of Asynchronous Control Circuits from Graph-Theoretic Specifications. IEEE Trans. on CAD, 11(11):1426-1438, Nov. 1992.
	22	Peter Vanbekbergen , Bill Lin , Gert Goosens , Hugo De Man, A generalized state assignment theory for transformation on signal transition graphs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.112-117, November 1992, Santa Clara, California, United States
	23	M. L. Yu and P. A. Subrahmanyam. A New Approach for Checking the Unique State Coding Property of Signal Transition Graphs. In Proc. of EDAC, pages 312-321, 1992.

CITED BY 2

	Prabhakar Kudva , Ganesh Gopalakrishnan , Hans Jacobson, A technique for synthesizing distributed burst-mode circuits, Proceedings of the 33rd annual conference on Design automation, p.67-70, June 03-07, 1996, Las Vegas, Nevada, United States
	Ruchir Puri , Jun Gu, A divide-and-conquer approach for asynchronous interface synthesis, Proceedings of the 7th international symposium on High-level synthesis, p.118-125, May 18-20, 1994, Niagra-on-the-Lake, Ontario, Canada