| Run-time generation of HPS microinstructions from a VAX instruction stream |
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International Symposium on Microarchitecture
archive
Proceedings of the 19th annual workshop on Microprogramming
table of contents
New York, New York, United States
Pages: 75 - 81
Year of Publication: 1986
ISBN:0-8186-0736-X
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Authors
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Y. N. Patt
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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S. W. Melvin
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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W. M. Hwu
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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M. C. Shebanow
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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C. Chen
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Computer Science Division, University of California, Berkeley, Berkeley, CA
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Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 7
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 ABSTRACT
The VAX architecture is a popular ISP architecture that has been implemented in several different technologies targeted to a wide range of performance specifications. However, it has been argued that the VAX has specific characteristics which preclude a very high performance implementation. We have developed a microarchitecture (HPS) which is specifically intended for implementing very high performance computing engines. Our model of execution is a restriction on fine granularity data flow. In this paper, we concentrate on one particular aspect of an HPS implementation of the VAX architecture: the generation of HPS microinstructions (i.e. data flow nodes) from a VAX instruction stream.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Anderson, D. W., Sparacio, F. J., Tomasulo, R. M., "The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling," IBM Journal of Research and Development, vol. 11, January, 1967, pp. 8-24.
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Y. N. Patt , W. M. Hwu , M. Shebanow, HPS, a new microarchitecture: rationale and introduction, Proceedings of the 18th annual workshop on Microprogramming, p.103-108, December 03-06, 1985, Pacific Grove, California, United States
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Y. N. Patt , S. W. Melvin , W. M. Hwu , M. C. Shebanow, Critical issues regarding HPS, a high performance microarchitecture, Proceedings of the 18th annual workshop on Microprogramming, p.109-116, December 03-06, 1985, Pacific Grove, California, United States
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Tomasulo, R. M., "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Research and Development, vol. 11, January, 1967, pp. 25-33.
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VAX Architecture Handbook, Digital Equipment Corporation, 1981.
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CITED BY 7
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S. W. Melvin , M. C. Shebanow , Y. N. Patt, Hardware support for large atomic units in dynamically scheduled machines, Proceedings of the 21st annual workshop on Microprogramming and microarchitecture, p.60-63, November 28-December 02, 1988, San Diego, California, United States
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James E. Wilson , Steve Melvin , Michael Shebanow , Wen-mei Hwu , Yale N. Patt, On tuning the microarchitecture of an HPS implementation of the VAX, Proceedings of the 20th annual workshop on Microprogramming, p.162-167, December 01-04, 1987, Colorado Springs, Colorado, United States
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A. Despain , Y. Patt , V. Srini , P. Bitar , W. Bush , C. Chien , W. Citrin , B. Fagin , W. Hwu , S. Melvin , R. McGeer , A. Singhal , M. Shebanow , P. Van Roy, Aquarius, ACM SIGARCH Computer Architecture News, v.15 n.1, p.22-34, March 1987
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