| Analysis of the conditional skip instructions of the HP precision architecture |
| Full text |
Pdf
(848 KB)
|
| Source
|
International Symposium on Microarchitecture
archive
Proceedings of the 27th annual international symposium on Microarchitecture
table of contents
San Jose, California, United States
Pages: 207 - 216
Year of Publication: 1994
ISBN:0-89791-707-3
|
|
Authors
|
|
Jonathan P. Vogel
|
Telxon Corporation, 3330 West Market Street, Akron, OH
|
|
Bruce K. Holmer
|
EECS Department, Northwestern University, 2145 Sheridan Road, Evanston, IL
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 3, Citation Count: 0
|
|
|
ABSTRACT
The HP-PA instruction set allows any arithmetic instruction to conditionally skip the following instruction based on the result of the arithmetic calculation. We have isolated this architectural feature and measured its performance benefit on a set of SPEC benchmark programs. Results indicate that adding the ability to skip to arithmetic instructions yields only a marginal performance benefit (less than 0.3%) for floating point intensive programs. For integer programs, however, the average benefit is between 0.6 and 2.8%. Most of this benefit comes from using arithmetic nullification with the COMICLR and COMCLR instructions. Our results assume a scalar processor, and therefore provide a lower bound on the performance benefit for more aggressive implementations.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
Tom Asprey , Gregory S. Averill , Eric DeLano , Russ Mason , Bill Weiner , Jeff Yetter, Performance Features of the PA7100 Microprocessor, IEEE Micro, v.13 n.3, p.22-35, May 1993
[doi> 10.1109/40.216746]
|
 |
2
|
Pohua P. Chang , Scott A. Mahlke , William Y. Chen , Nancy J. Warter , Wen-mei W. Hwu, IMPACT: an architectural framework for multiple-instruction-issue processors, Proceedings of the 18th annual international symposium on Computer architecture, p.266-275, May 27-30, 1991, Toronto, Ontario, Canada
|
| |
3
|
|
| |
4
|
|
| |
5
|
K. W. Pettis and W. B. Buzbee. Hewlett- Packard Precision Architecture compiler performance. Hewlett-Packard Journal, pages 29-37, Mar. 1987.
|
| |
6
|
|
| |
7
|
J. P. Vogel. Performance analysis of conditionally nullifying arithmetic instructions in the Hewlett- Packard Precision Architecture. Master's thesis, Northwestern University, 1993.
|
|