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Iterative modulo scheduling: an algorithm for software pipelining loops
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Source International Symposium on Microarchitecture archive
Proceedings of the 27th annual international symposium on Microarchitecture table of contents
San Jose, California, United States
Pages: 63 - 74  
Year of Publication: 1994
ISBN:0-89791-707-3
Author
B. Ramakrishna Rau  Hewlett-Packard Laboratories, 1501 Page Mill Road, Bldg. 3L, Palo Alto, CA
Sponsors
IEEE-CS\TCMM : TC on Microprocessors & Microcomputers
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
ACM  New York, NY, USA
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ABSTRACT

Modulo scheduling is a framework within which a wide variety of algorithms and heuristics may be defined for software pipelining innermost loops. This paper presents a practical algorithm, iterative modulo scheduling, that is capable of dealing with realistic machine models. This paper also characterizes the algorithm in terms of the quality of the generated schedules as well the computational expense incurred.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY  131
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 


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