| Design and implementation of transactional constructs for C/C++ |
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Conference on Object Oriented Programming Systems Languages and Applications
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Proceedings of the 23rd ACM SIGPLAN conference on Object-oriented programming systems languages and applications
table of contents
Nashville, TN, USA
SESSION: Concurrency
table of contents
Pages 195-212
Year of Publication: 2008
ISBN:978-1-60558-215-3
Also published in ...
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Authors
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Yang Ni
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Intel Corporation, Santa Clara, CA, USA
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Adam Welc
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Intel Corporation, Santa Clara, CA, USA
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Ali-Reza Adl-Tabatabai
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Intel Corporation, Santa Clara, CA, USA
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Moshe Bach
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Intel Corporation, Haifa, Israel
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Sion Berkowits
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Intel Corporation, Haifa, Israel
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James Cownie
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Intel Corporation, Glasgow, United Kingdom
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Robert Geva
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Intel Corporation, Santa Clara, CA, USA
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Sergey Kozhukow
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Intel Corporation, Novosibirsk, Russian Fed.
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Ravi Narayanaswamy
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Intel Corporation, Santa Clara, CA, USA
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Jeffrey Olivier
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Intel Corporation, Champaign, IL, USA
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Serguei Preis
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Intel Coporation, Novosibirsk, Russian Fed.
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Bratin Saha
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Intel Corporation, Santa Clara, CA, USA
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Ady Tal
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Intel Corporation, Haifa, Israel
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Xinmin Tian
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Intel Corporation, Santa Clara, CA, USA
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Downloads (6 Weeks): 27, Downloads (12 Months): 280, Citation Count: 5
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ABSTRACT
This paper presents a software transactional memory system that introduces first-class C++ language constructs for transactional programming. We describe new C++ language extensions, a production-quality optimizing C++ compiler that translates and optimizes these extensions, and a high-performance STM runtime library. The transactional language constructs support C++ language features including classes, inheritance, virtual functions, exception handling, and templates. The compiler automatically instruments the program for transactional execution and optimizes TM overheads. The runtime library implements multiple execution modes and implements a novel STM algorithm that supports both optimistic and pessimistic concurrency control. The runtime switches a transaction's execution mode dynamically to improve performance and to handle calls to precompiled functions and I/O libraries. We present experimental results on 8 cores (two quad-core CPUs) running a set of 20 non-trivial parallel programs. Our measurements show that our system scales well as the numbers of cores increases and that our compiler and runtime optimizations improve scalability.
REFERENCES
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CITED BY 7
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Haris Volos , Adam Welc , Ali-Reza Adl-Tabatabai , Tatiana Shpeisman , Xinmin Tian , Ravi Narayanaswamy, NePalTM: design and implementation of nested parallelism for transactional memory systems, Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming, February 14-18, 2009, Raleigh, NC, USA
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Ferad Zyulkyarov , Adrian Cristal , Sanja Cvijic , Eduard Ayguade , Mateo Valero , Osman Unsal , Tim Harris, WormBench: a configurable workload for evaluating transactional memory systems, Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture, p.61-68, October 26-26, 2008, Toronto, Canada
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Ferad Zyulkyarov , Vladimir Gajinov , Osman S. Unsal , Adrián Cristal , Eduard Ayguadé , Tim Harris , Mateo Valero, Atomic quake: using transactional memory in an interactive multiplayer game server, Proceedings of the 14th ACM SIGPLAN symposium on Principles and practice of parallel programming, February 14-18, 2009, Raleigh, NC, USA
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Haris Volos , Andres Jaan Tack , Neelam Goyal , Michael M. Swift , Adam Welc, xCalls: safe I/O in memory transactions, Proceedings of the fourth ACM european conference on Computer systems, April 01-03, 2009, Nuremberg, Germany
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