ACM Portal
  Subscribe (Full Service)    Register (Limited Service, Free)    Login
  Search:   The ACM Digital Library   The Guide
  
ACM Home Page
Please provide us with feedback. Feedback
Register traffic analysis for streamlining inter-operation communication in fine-grain parallel processors
Full text PdfPdf (1.31 MB)
Source International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents
Portland, Oregon, United States
Pages: 236 - 245  
Year of Publication: 1992
ISBN:0-8186-3175-9
Also published in ...
Authors
Manoj Franklin
Gurindar S. Sohi
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 18,   Citation Count: 24
Additional Information:

references   cited by   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/144953.145818
What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
R. R. Oehler , R. D. Groves, IBM RISC System/6000 processor architecture, IBM Journal of Research and Development, v.34 n.1, p.23-36, Jan. 1990
2
J. R. Goodman , Jian-tu Hsieh , Koujuch Liou , Andrew R. Pleszkun , P. B. Schechter , Honesty C. Young, PIPE: a VLSI decoupled architecture, Proceedings of the 12th annual international symposium on Computer architecture, p.20-27, June 17-19, 1985, Boston, Massachusetts, United States
 
3
M. Annaratone , E. Arnould , T. Gross , H. T. Kung , M. Lam, The warp computer: Architecture, implementation, and performance, IEEE Transactions on Computers, v.36 n.12, p.1523-1538, Dec. 1987
4
Michael Butler , Tse-Yu Yeh , Yale Patt , Mitch Alsup , Hunter Scales , Michael Shebanow, Single instruction stream parallelism is greater than two, Proceedings of the 18th annual international symposium on Computer architecture, p.276-286, May 27-30, 1991, Toronto, Ontario, Canada
 
5
Robert P. Colwell , Robert P. Nix , John J. O'Donnell , David B. Papworth , Paul K. Rodman, A VLIW architecture for a trace Scheduling Compiler, IEEE Transactions on Computers, v.37 n.8, p.967-979, August 1988  [doi>10.1109/12.2247]
 
6
Robert P. Colwell , W. Eric Hall , Chandra S. Joshi , David B. Papworth , Paul K. Rodman , James E. Tornes, Architecture and implementation of a VLIW supercomputer, Proceedings of the 1990 conference on Supercomputing, p.910-919, October 1990, New York, New York, United States
7
Shekhar Borkar , Robert Cohn , George Cox , Thomas Gross , H. T. Kung , Monica Lam , Margie Levine , Brian Moore , Wire Moore , Craig Peterson , Jim Susman , Jim Sutton , John Urbanski , Jon Webb, Supporting systolic and memory communication in iWarp, Proceedings of the 17th annual international symposium on Computer Architecture, p.70-81, May 28-31, 1990, Seattle, Washington, United States
8
Todd M. Austin , Gurindar S. Sohi, Dynamic dependency analysis of ordinary programs, Proceedings of the 19th annual international symposium on Computer architecture, p.342-351, May 19-21, 1992, Queensland, Australia
9
Manoj Franklin , Gurindar S. Sohi, The expandable split window paradigm for exploiting fine-grain parallelsim, Proceedings of the 19th annual international symposium on Computer architecture, p.58-67, May 19-21, 1992, Queensland, Australia
 
10
David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
 
11
E. Hokenek, R. K. Montoye, and P. W. Cook, "Second-Generation RISC Floating Point with Multiply-Add Fused," IEEE J. of Solid-State Circuits, vol. 25, pp. 1207-1213, October 1990.
 
12
R. Jolly, "A 9-ns 1.4 Gigabyteds, 17-Ported CMOS Register File," IEEE J. of Solid-State Circuits, vol. 26, pp. 1407-1412, October 1991.
 
13
G. Kane, MIPS R2000 RiSC Architec~'ure. Englewood Cliffs, New Jersey: Prentice Hall, 1987.
14
K. Murakami , N. Irie , S. Tomita, SIMP (Single Instruction stream/Multiple instruction Pipelining): a novel high-speed single-processor architecture, Proceedings of the 16th annual international symposium on Computer architecture, p.78-85, April 1989, Jerusalem, Israel
 
15
B. Ramakrishna Rau , David W. L. Yen , Wei Yen , Ross A. Towie, The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-Offs, Computer, v.22 n.1, p.12-26, 28-30, 32-35, January 1989  [doi>10.1109/2.19820]
16
Richard M. Russell, The CRAY-1 computer system, Communications of the ACM, v.21 n.1, p.63-72, Jan. 1978  [doi>10.1145/359327.359336]
17
James E. Smith, Decoupled access/execute computer architectures, Proceedings of the 9th annual symposium on Computer Architecture, p.112-119, April 26-29, 1982, Austin, Texas, United States
 
18
James E. Smith , Andrew R. Pleszkun, Implementing Precise Interrupts in Pipelined Processors, IEEE Transactions on Computers, v.37 n.5, p.562-573, May 1988  [doi>10.1109/12.4607]
19
Andrew Wolfe , John P. Shen, A variable instruction stream extension to the VLIW architecture, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.2-14, April 08-11, 1991, Santa Clara, California, United States

CITED BY  24
Gurindar S. Sohi, Retrospective: instruction issue logic for high-performance, interruptable pipelined processors, 25 years of the international symposia on Computer architecture (selected papers), p.51-53, June 27-July 02, 1998, Barcelona, Spain
Gurindar Sohi, Retrospective: multiscalar processors, 25 years of the international symposia on Computer architecture (selected papers), p.111-114, June 27-July 02, 1998, Barcelona, Spain
Narayan Ranganathan , Manoj Franklin, An empirical study of decentralized ILP execution models, ACM SIGPLAN Notices, v.33 n.11, p.272-281, Nov. 1998
Sriram Vajapeyam , Tulika Mitra, Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences, ACM SIGARCH Computer Architecture News, v.25 n.2, p.1-12, May 1997
Scott E. Breach , T. N. Vijaykumar , Gurindar S. Sohi, The anatomy of the register file in a multiscalar processor, Proceedings of the 27th annual international symposium on Microarchitecture, p.181-190, November 30-December 02, 1994, San Jose, California, United States
 
J. Adam Butts , Gurindar S. Sohi, Characterizing and predicting value degree of use, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
 
Luis A. Lozano , Guang R. Gao, Exploiting short-lived variables in superscalar processors, Proceedings of the 28th annual international symposium on Microarchitecture, p.292-302, November 29-December 01, 1995, Ann Arbor, Michigan, United States
Gurhan Kucuk , Dmitry Ponomarev , Oguz Ergin , Kanad Ghose, Reducing reorder buffer complexity through selective operand caching, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
Hans Vandierendonck , Philippe Manet , Thibault Delavallee , Igor Loiselle , Jean-Didier Legat, By-passing the out-of-order execution pipeline to increase energy-efficiency, Proceedings of the 4th international conference on Computing frontiers, May 07-09, 2007, Ischia, Italy
Kenneth Hoste , Aashish Phansalkar , Lieven Eeckhout , Andy Georges , Lizy K. John , Koen De Bosschere, Performance prediction based on inherent program similarity, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
 
Oguz Ergin , Deniz Balkan , Kanad Ghose , Dmitry Ponomarev, Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.304-315, December 04-08, 2004, Portland, Oregon
 
Dmitry Ponomarev , Gurhan Kucuk , Oguz Ergin , Kanad Ghose, Isolating Short-Lived Operands for Energy Reduction, IEEE Transactions on Computers, v.53 n.6, p.697-709, June 2004
 
Jack L. Lo , Sujay S. Parekh , Susan J. Eggers , Henry M. Levy , Dean M. Tullisen, Software-Directed Register Deallocation for Simultaneous Multithreaded Processors, IEEE Transactions on Parallel and Distributed Systems, v.10 n.9, p.922-933, September 1999
Hui Zeng , Kanad Ghose, Register file caching for energy efficiency, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
 
Milo M. Martin , Amir Roth , Charles N. Fischer, Exploiting dead value information, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.125-135, December 01-03, 1997, Research Triangle Park, North Carolina, United States
Francis Tseng , Yale N. Patt, Achieving Out-of-Order Performance with Almost In-Order Complexity, ACM SIGARCH Computer Architecture News, v.36 n.3, p.3-12, June 2008
 
Lieven Eeckhout , Tom Vander Aa , Bart Goeman , Hans Vandierendonck , Rudy Lauwereins , Koen De Bosschere, Application domains for fixed-length block structured architectures, Australian Computer Science Communications, v.23 n.4, p.35-44, January 2001
 
Eric Hao , Po-Yung Chang , Marius Evers , Yale N. Patt, Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures, International Journal of Parallel Programming, v.26 n.4, p.449-478, August 1998
 
Deniz Balkan , Joseph Sharkey , Dmitry V. Ponomarev , Kanad Ghose, Predicting and Exploiting Transient Values for Reducing Register File Pressure and Energy Consumption, IEEE Transactions on Computers, v.57 n.1, p.82-95, January 2008
Ho-Seop Kim , James E. Smith, An instruction set and microarchitecture for instruction level distributed processing, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
Deniz Balkan , Joseph Sharkey , Dmitry Ponomarev , Kanad Ghose, SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
 
Josep Llosa , Mateo Valero , Eduard Ayguadé, Heuristics for register-constrained software pipelining, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.250-261, December 02-04, 1996, Paris, France
Daniel Citron , Dror Feitelson , Larry Rudolph, Accelerating multi-media processing by implementing memoing in multiplication and division units, ACM SIGPLAN Notices, v.33 n.11, p.252-261, Nov. 1998
 
Venkata Krishnan , Josep Torrellas, The Need for Fast Communication in Hardware-Based Speculative Chip Multiprocessors, International Journal of Parallel Programming, v.29 n.1, p.3-33, February 2001

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Styles (e.g., parallel, pipeline, special-purpose)

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.2 Design Aids
          Subjects: Simulation

  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Parallel processors**


General Terms:
Design, Performance

Collaborative Colleagues:
Manoj Franklin: colleagues
Gurindar S. Sohi: colleagues

Peer to Peer - Readers of this Article have also read:
This Article has also been published in:

The ACM Portal is published by the Association for Computing Machinery. Copyright © 2009 ACM, Inc.
Terms of Usage   Privacy Policy   Code of Ethics   Contact Us

Useful downloads: Adobe Acrobat    QuickTime    Windows Media Player    Real Player