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The effect of page allocation on caches
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Source International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents
Portland, Oregon, United States
Pages: 222 - 225  
Year of Publication: 1992
ISBN:0-8186-3175-9
Also published in ...
Authors
William L. Lynch
Brian K. Bray
M. J. Flynn
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 15,   Citation Count: 8
Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
Peter J. Denning, Virtual Memory, ACM Computing Surveys (CSUR), v.2 n.3, p.153-189, Sept. 1970  [doi>10.1145/356571.356573]
2
Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982  [doi>10.1145/356887.356892]
 
3
Mark D. Hill, A Case for Direct-Mapped Caches, Computer, v.21 n.12, p.25-40, December 1988  [doi>10.1109/2.16187]
 
4
Sunil Mirapuri , Michael Woodacre , Nader Vasseghi, The Mips R4000 Processor, IEEE Micro, v.12 n.2, p.10-22, March 1992  [doi>10.1109/40.127580]
 
5
G. F. Grohoski, J. A. Kahle, L. E. Thatcher, and C. R. Moore, BISC System/6000 Technology, ch. Branch and Fixed-Point Instruction Execution Units, pp. 24-30. IBM Corp, 90.
 
6
G. Blanck and S. Krueger, "Super Sparc, A Fully Integrated Superscalar Processor," in Hot Chips lII, pp. 1-5, August 91.
 
7
R. Cheng, "Virtual Address Cache in UNIX," in Usenix Conference .Proceedings, pp. 217-224, June 87.
 
8
J. Moussouris et aI., "A CMOS RISC Processor With Integrated System Functions," Compcon, pp. 126-131, Spring 86.
9
R. L. Sites , A. Agarwal, Multiprocessor cache analysis using ATUM, Proceedings of the 15th Annual International Symposium on Computer architecture, p.186-195, May 30-June 02, 1988, Honolulu, Hawaii, United States
 
10
R. Kessler and M. Hill, "Miss Reduction in Large Real-Indexed Caches," Technical Report No. 940, Department of Computer Science, University of Wisconsin-Madison, June 90.
 
11
R. E. Kessler, "Analysis of Mulit-Megabyte Secondary CPU Cache Memories," Computer Science Technical Report 1032, University of Wisconsin -Madison, July 91.
 
12
William L. Lynch , Michael J. Flynn, Paging Performance with Page Coloring., Stanford University, Stanford, CA, 1991
13
George Taylor , Peter Davies , Michael Farmwald, The TLB slice—a low-cost high-speed address translation mechanism, Proceedings of the 17th annual international symposium on Computer Architecture, p.355-363, May 28-31, 1990, Seattle, Washington, United States

CITED BY  8
 
Jun Nakajima , Venkatesh Pallipadi, Enhancements for hyper-threading technology in the operating system: seeking the optimal scheduling, Proceedings of the 2nd conference on Industrial Experiences with Systems Software, p.3-3, December 08, 2002, Boston, MA
Satyendra Bahadur , Viswanathan Kalyanakrishnan , James Westall, An empirical study of the effects of careful page placement in Linux, Proceedings of the 36th annual Southeast regional conference, p.241-250, April 1998
Thomas J. Murray , A. Wayne Madison , James M. Westall, Lookahead page placement, Proceedings of the 33rd annual on Southeast regional conference, March 17-18, 1995, Clemson, South Carolina
André Seznec, A case for two-way skewed-associative caches, ACM SIGARCH Computer Architecture News, v.21 n.2, p.169-178, May 1993
 
Rui Min , Yiming Hu, Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses, IEEE Transactions on Computers, v.50 n.11, p.1191-1201, November 2001
 
Livio Soares , David Tam , Michael Stumm, Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.258-269, November 08-12, 2008
Brad Calder , Chandra Krintz , Simmi John , Todd Austin, Cache-conscious data placement, ACM SIGPLAN Notices, v.33 n.11, p.139-149, Nov. 1998
Reza Azimi , David K. Tam , Livio Soares , Michael Stumm, Enhancing operating system support for multicore processors by using hardware performance monitoring, ACM SIGOPS Operating Systems Review, v.43 n.2, April 2009

INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Virtual memory
      B.3.3 Performance Analysis and Design Aids**
          Subjects: Simulation**


General Terms:
Algorithms, Design, Performance


Keywords:
cache, page allocation, page coloring, virtual memory

Collaborative Colleagues:
William L. Lynch: colleagues
Brian K. Bray: colleagues
M. J. Flynn: colleagues

Peer to Peer - Readers of this Article have also read:
This Article has also been published in:

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