Translation hint buffers to reduce access time of physically-addressed instruction caches

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Translation hint buffers to reduce access time of physically-addressed instruction caches

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International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents

Portland, Oregon, United States

Pages: 206 - 209

Year of Publication: 1992

ISBN:0-8186-3175-9

Also published in ...

Authors

Brian K. Bray
Michael J. Flynn

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 8, Citation Count: 1

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Bulent Abali. A Parallel Address Translation Mechanism For Microprocessors. Technical Report No. RC 13101, IBM Watson Research Center, September 1987.
	2	Brian Bray and M. J. Flynn. Translation Hint Buffers To Reduce Access Time Of Physically-Addressed Instruction Caches. Technical Report No. CSL-TR-92-535, Computer Systems Laboratory, Stanford University, August 1992.
	3	J. Bradley Chen , Anita Borg , Norman P. Jouppi, A simulation based study of TLB performance, Proceedings of the 19th annual international symposium on Computer architecture, p.114-123, May 19-21, 1992, Queensland, Australia
	4	Douglas W. Clark , Joel S. Emer, Performance of the VAX-11/780 translation buffer: simulation and measurement, ACM Transactions on Computer Systems (TOCS), v.3 n.1, p.31-62, Feb. 1985 [doi>10.1145/214451.214455]
	5	K. Hua et al. Early Resolution of Address Translation in Cache Design. In International Con}erence On Computer Design: VLSI In Computers and Processors, pages 408-412, September 1990.
	6	T. Kilburn, D. Edwards, M. Lanigan, and F. Sumner. One- Level Storage System. IRE Transactions, EC-11(2):223-235, April 1962.
	7	J. Lee and A. J. Smith. Branch Prediction Strategies and Branch Target Buffer Design. IEEE Computer, 17(1):6-22, January 1984.
	8	J. Moussouris et al. A CMOS RISC Processor With Integrated System Functions. In Compcon, pages 126-131, Spring 1986.
	9	George Taylor , Peter Davies , Michael Farmwald, The TLB slice—a low-cost high-speed address translation mechanism, Proceedings of the 17th annual international symposium on Computer Architecture, p.355-363, May 28-31, 1990, Seattle, Washington, United States

CITED BY

Todd M. Austin , Gurindar S. Sohi, High-bandwidth address translation for multiple-issue processors, ACM SIGARCH Computer Architecture News, v.24 n.2, p.158-167, May 1996

INDEX TERMS

Primary Classification:
B. Hardware
B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
B.1.5 Microcode Applications
Subjects: Instruction set interpretation

Additional Classification:
B. Hardware
B.3 MEMORY STRUCTURES
B.3.2 Design Styles
Subjects: Cache memories

C. Computer Systems Organization
C.0 GENERAL
Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

General Terms:
Design, Performance

Keywords:
cache, physical address, translation lookaside buffer, virtual address, virtual memory

Collaborative Colleagues:

Brian K. Bray: colleagues

Michael J. Flynn: colleagues

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This Article has also been published in:

ACM SIGMICRO Newsletter
Volume 23 , Issue 1-2 Dec. 1992

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