Code scheduling for VLIW/superscalar processors with limited register files

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Code scheduling for VLIW/superscalar processors with limited register files

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International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents

Portland, Oregon, United States

Pages: 197 - 201

Year of Publication: 1992

ISBN:0-8186-3175-9

Also published in ...

Authors

Tokuzo Kiyohara
John C. Gyllenhaal

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 10, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	S. A. Mahlke , W. Y. Chen , J. C. Gyllenhaal , W.-M. W. Hwu, Compiler code transformations for superscalar-based high performance systems, Proceedings of the 1992 ACM/IEEE conference on Supercomputing, p.808-817, November 16-20, 1992, Minneapolis, Minnesota, United States
	2	W. W. Hwu , P. P. Chang, Exploiting parallel microprocessor microarchitectures with a compiler code generator, Proceedings of the 15th Annual International Symposium on Computer architecture, p.45-53, May 30-June 02, 1988, Honolulu, Hawaii, United States
	3	J. R. Goodman , W.-C. Hsu, Code scheduling and register allocation in large basic blocks, Proceedings of the 2nd international conference on Supercomputing, p.442-452, June 1988, St. Malo, France [doi>10.1145/55364.55407]
	4	Freudenberger, S. and Ruttenberg, J., "Phase Ordering of Register Allocation and Instruction Scheduling," in Code Generation- Concepts, Tools, Techniques, Dagstuhl, Germany, May 1991.
	5	Edward G. Coffman, Jr., ed., Computer and Job/Shop Scheduling Theory. John WHey g~ Sons, 1976.
	6	John R. Ellis, Bulldog: a compiler for VLSI architectures, MIT Press, Cambridge, MA, 1986
	7	Pohua P. Chang , Scott A. Mahlke , William Y. Chen , Nancy J. Warter , Wen-mei W. Hwu, IMPACT: an architectural framework for multiple-instruction-issue processors, Proceedings of the 18th annual international symposium on Computer architecture, p.266-275, May 27-30, 1991, Toronto, Ontario, Canada

CITED BY 2

	William R. Mark , Kekoa Proudfoot, Compiling to a VLIW fragment pipeline, Proceedings of the ACM SIGGRAPH/EUROGRAPHICS workshop on Graphics hardware, p.47-56, August 2001, Los Angeles, California, United States
	Christoph Keßler , Andrzej Bednarski, A Dynamic Programming Approach to Optimal Integrated Code Generation, ACM SIGPLAN Notices, v.36 n.8, p.165-174, Aug. 2001

INDEX TERMS

Primary Classification:
B. Hardware
B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION

Additional Classification:
B. Hardware
B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
B.1.5 Microcode Applications
Subjects: Instruction set interpretation

F. Theory of Computation
F.2 ANALYSIS OF ALGORITHMS AND PROBLEM COMPLEXITY
F.2.2 Nonnumerical Algorithms and Problems
Subjects: Sequencing and scheduling

General Terms:
Algorithms, Design, Experimentation, Performance

Collaborative Colleagues:

Tokuzo Kiyohara: colleagues

John C. Gyllenhaal: colleagues

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This Article has also been published in:

ACM SIGMICRO Newsletter
Volume 23 , Issue 1-2 Dec. 1992

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