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Stride directed prefetching in scalar processors
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Source International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents
Portland, Oregon, United States
Pages: 102 - 110  
Year of Publication: 1992
ISBN:0-8186-3175-9
Also published in ...
Authors
John W. C. Fu
Janak H. Patel
Bob L. Janssens
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
Bibliometrics
Downloads (6 Weeks): 6,   Downloads (12 Months): 61,   Citation Count: 57
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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John W. C. Fu , Janak H. Patel, Data prefetching in multiprocessor vector cache memories, Proceedings of the 18th annual international symposium on Computer architecture, p.54-63, May 27-30, 1991, Toronto, Ontario, Canada
 
Jans91
B.L. Janssens, "Generation of Mulfiprocessor Address Traces and their use in the Performance Analysis of Cache-based Error Recovery Methods," Tech. Rpt. CRHC-91-10, Center for Reliable and High Performance Computing, University of Illinois, May 1991.
Przy90
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Skle92
Ivan Sklenar, Prefetch unit for vector operations on scalar computers (abstract), Proceedings of the 19th annual international symposium on Computer architecture, p.430, May 19-21, 1992, Queensland, Australia
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CITED BY  57
Ilya Ganusov , Martin Burtscher, Efficient emulation of hardware prefetchers via event-driven helper threading, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
 
Zhong Wang , Timothy W. O'neil , Edwin H.-M. Sha, Minimizing Average Schedule Length under Memory Constraints by Optimal Partitioning and Prefetching, Journal of VLSI Signal Processing Systems, v.27 n.3, p.215-233, March 1, 2001
Y. Jégou , O. Temam, Speculative prefetching, Proceedings of the 7th international conference on Supercomputing, p.57-66, July 19-23, 1993, Tokyo, Japan
 
Xie Yuejian , Zhang Youhui , Wang Dongsheng, Heterogeneous associative cache for multimedia applications, IASTED European Conference on Proceedings of the IASTED European Conference: internet and multimedia systems and applications, p.100-105, March 14-16, 2007, Chamonix, France
Ronald G. Dreslinski , Ali G. Saidi , Trevor Mudge , Steven K. Reinhardt, Analysis of hardware prefetching across virtual page boundaries, Proceedings of the 4th international conference on Computing frontiers, May 07-09, 2007, Ischia, Italy
Ilya Ganusov , Martin Burtscher, Future execution: A prefetching mechanism that uses multiple cores to speed up single threads, ACM Transactions on Architecture and Code Optimization (TACO), v.3 n.4, p.424-449, December 2006
 
Xiaotong Zhuang , Hsien-Hsin S. Lee, Reducing Cache Pollution via Dynamic Data Prefetch Filtering, IEEE Transactions on Computers, v.56 n.1, p.18-31, January 2007
S. Palacharla , R. E. Kessler, Evaluating stream buffers as a secondary cache replacement, ACM SIGARCH Computer Architecture News, v.22 n.2, p.24-33, April 1994
Jaeheon Jeong , Per Stenström , Michel Dubois, Simple penalty-sensitive replacement policies for caches, Proceedings of the 3rd conference on Computing frontiers, May 03-05, 2006, Ischia, Italy
Ben Juurlink, Approximating the optimal replacement algorithm, Proceedings of the 1st conference on Computing frontiers, April 14-16, 2004, Ischia, Italy
Michael K. Gschwind , Thomas J. Pietsch, Vector prefetching, ACM SIGARCH Computer Architecture News, v.23 n.5, p.1-7, Dec. 1995
 
Tien-Fu Chen, An effective programmable prefetch engine for on-chip caches, Proceedings of the 28th annual international symposium on Microarchitecture, p.237-242, November 29-December 01, 1995, Ann Arbor, Michigan, United States
 
Oliver Temam, An Algorithm for Optimally Exploiting Spatial and Temporal Locality in Upper Memory Levels, IEEE Transactions on Computers, v.48 n.2, p.150-158, February 1999
Koray Öner , Michel Dubois, Effects of memory latencies on non-blocking processor/cache architectures, Proceedings of the 7th international conference on Supercomputing, p.338-347, July 19-23, 1993, Tokyo, Japan
 
Hassan Sbeyti , Smail Niar , Lieven Eeckhout, Pattern-driven prefetching for multimedia applications on embedded processors, Journal of Systems Architecture: the EUROMICRO Journal, v.52 n.4, p.199-212, April 2006
Ilya Ganusov , Martin Burtscher, On the importance of optimizing the configuration of stream prefetchers, Proceedings of the 2005 workshop on Memory system performance, June 12-12, 2005, Chicago, Illinois
 
Edward H. Gornish , Alexander Veidenbaum, An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors, International Journal of Parallel Programming, v.27 n.1, p.35-70, Feb. 1999
James Dundas , Trevor Mudge, Improving data cache performance by pre-executing instructions under a cache miss, Proceedings of the 11th international conference on Supercomputing, p.68-75, July 07-11, 1997, Vienna, Austria
Nathalie Drach, Hardware implementation issues of data prefetching, Proceedings of the 9th international conference on Supercomputing, p.245-254, July 03-07, 1995, Barcelona, Spain
 
James E. Bennett , Michael J. Flynn, Prediction caches for superscalar processors, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.81-90, December 01-03, 1997, Research Triangle Park, North Carolina, United States
 
Shlomit S. Pinter , Adi Yoaz, Tango: a hardware-based data prefetching technique for superscalar processors, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.214-225, December 02-04, 1996, Paris, France
Antonio González , Carlos Aliagas , Mateo Valero, A data cache with multiple caching strategies tuned to different types of locality, Proceedings of the 9th international conference on Supercomputing, p.338-347, July 03-07, 1995, Barcelona, Spain
 
Daniel Gracia Perez , Gilles Mouchard , Olivier Temam, MicroLib: A Case for the Quantitative Comparison of Micro-Architecture Mechanisms, Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, p.43-54, December 04-08, 2004, Portland, Oregon
 
Tzi-Cker Chiueh, Sunder: a programmable hardware prefetch architecture for numerical loops, Proceedings of the 1994 conference on Supercomputing, p.488-497, December 1994, Washington, D.C., United States
Tzi-cker Chiueh, Sunder: a programmable hardware prefetch architecture for numerical loops, Proceedings of the 1994 ACM/IEEE conference on Supercomputing, November 14-18, 1994, Washington, D.C.
Olivier Temam, Investigating optimal local memory performance, ACM SIGPLAN Notices, v.33 n.11, p.218-227, Nov. 1998
T.-F. Chen , J.-L. Baer, A performance study of software and hardware data prefetching schemes, ACM SIGARCH Computer Architecture News, v.22 n.2, p.223-232, April 1994
Marius Pirvu , Laxmi Bhuyan, Hardware spatial forwarding for widely shared data, Proceedings of the 14th international conference on Supercomputing, p.264-273, May 08-11, 2000, Santa Fe, New Mexico, United States
R. Manikantan , R. Govindarajan, Focused prefetching: performance oriented prefetching based on commit stalls, Proceedings of the 22nd annual international conference on Supercomputing, June 07-12, 2008, Island of Kos, Greece
Qin Zhao , Rodric Rabbah , Weng-Fai Wong, Dynamic memory optimization using pool allocation and prefetching, ACM SIGARCH Computer Architecture News, v.33 n.5, December 2005
 
Jean-Loup Baer , Tien-Fu Chen, Effective Hardware-Based Data Prefetching for High-Performance Processors, IEEE Transactions on Computers, v.44 n.5, p.609-623, May 1995
Jin-Ho Lee , Min-Young Lee , Seong-Uk Choi , Myong-Soon Park, Reducing cache conflicts in data cache prefetching, ACM SIGARCH Computer Architecture News, v.22 n.4, p.71-77, Sept. 1994
Seungryul Choi , Nicholas Kohout , Sumit Pamnani , Dongkeun Kim , Donald Yeung, A general framework for prefetch scheduling in linked data structures and its application to multi-chain prefetching, ACM Transactions on Computer Systems (TOCS), v.22 n.2, p.214-280, May 2004
 
Teresa L. Johnson , Matthew C. Merten , Wen-Mei W. Hwu, Run-time spatial locality detection and optimization, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.57-64, December 01-03, 1997, Research Triangle Park, North Carolina, United States
 
Andrew S. Huang , John P. Shen, A limit study of local memory requirements using value reuse profiles, Proceedings of the 28th annual international symposium on Microarchitecture, p.71-81, November 29-December 01, 1995, Ann Arbor, Michigan, United States
Pablo Ibáñez , Víctor Viñals , José L. Briz , María J. Garzarán, Characterization and improvement of load/store cache-based prefetching, Proceedings of the 12th international conference on Supercomputing, p.369-376, July 1998, Melbourne, Australia
Luddy Harrison, Examination of a memory access classification scheme for pointer-intensive and numeric programs, Proceedings of the 10th international conference on Supercomputing, p.133-140, May 25-28, 1996, Philadelphia, Pennsylvania, United States
 
Li Liu , Eric Li , Yimin Zhang , Zhizhong Tang, Optimization of frequent itemset mining on multiple-core processor, Proceedings of the 33rd international conference on Very large data bases, September 23-27, 2007, Vienna, Austria
 
Fredrik Dahlgren , Per Stenström, Evaluation of Hardware-Based Stride and Sequential Prefetching in Shared-Memory Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v.7 n.4, p.385-398, April 1996
Zhen Yang , Xudong Shi , Feiqi Su , Jih-Kwon Peir, Overlapping dependent loads with addressless preload, Proceedings of the 15th international conference on Parallel architectures and compilation techniques, September 16-20, 2006, Seattle, Washington, USA
José González , Antonio González, Speculative execution via address prediction and data prefetching, Proceedings of the 11th international conference on Supercomputing, p.196-203, July 07-11, 1997, Vienna, Austria
Keith I. Farkas , Paul Chow , Norman P. Jouppi , Zvonko Vranesic, Memory-system design considerations for dynamically-scheduled processors, ACM SIGARCH Computer Architecture News, v.25 n.2, p.133-143, May 1997
Chia-Lin Yang , Alvin R. Lebeck , Hung-Wei Tseng , Chien-Hao Lee, Tolerating memory latency through push prefetching for pointer-intensive applications, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.4, p.445-475, December 2004
 
Nathalie Drach , Jean-Luc Béchennec , Olivier Temam, Increasing hardware data prefetching performance using the second-level cache, Journal of Systems Architecture: the EUROMICRO Journal, v.48 n.4-5, p.137-149, December 2002
Gokul B. Kandiraju , Anand Sivasubramaniam, Going the distance for TLB prefetching: an application-driven study, ACM SIGARCH Computer Architecture News, v.30 n.2, May 2002
Doug Burger , James R. Goodman , Alain Kägi, Memory bandwidth limitations of future microprocessors, ACM SIGARCH Computer Architecture News, v.24 n.2, p.78-89, May 1996
Rodric M. Rabbah , Hariharan Sandanagobalane , Mongkol Ekpanyapong , Weng-Fai Wong, Compiler orchestrated prefetching via speculation and predication, ACM SIGPLAN Notices, v.39 n.11, November 2004
 
Henk Muller , Dan Page , James Irwin , David May, Caches with compositional performance, Embedded processor design challenges: systems, architectures, modeling, and simulation-SAMOS, Springer-Verlag New York, Inc., New York, NY, 2002
 
A. Mahjur , A. H. Jahangir , A. H. Gholamipour, On the performance of trace locality of reference, Performance Evaluation, v.60 n.1-4, p.51-72, May 2005
 
Teresa L. Johnson , Daniel A. Connors , Matthew C. Merten , Wen-mei W. Hwu, Run-Time Cache Bypassing, IEEE Transactions on Computers, v.48 n.12, p.1338-1354, December 1999
Abdel-Hameed A. Badawy , Aneesh Aggarwal , Donald Yeung , Chau-Wen Tseng, Evaluating the impact of memory system performance on software prefetching and locality optimizations, Proceedings of the 15th international conference on Supercomputing, p.486-500, June 2001, Sorrento, Italy
Freddy Gabbay , Avi Mendelson, Using value prediction to increase the power of speculative execution hardware, ACM Transactions on Computer Systems (TOCS), v.16 n.3, p.234-270, Aug. 1998
Sorin Iacobovici , Lawrence Spracklen , Sudarshan Kadambi , Yuan Chou , Santosh G. Abraham, Effective stream-based and execution-based data prefetching, Proceedings of the 18th annual international conference on Supercomputing, June 26-July 01, 2004, Malo, France
Steven P. Vanderwiel , David J. Lilja, Data prefetch mechanisms, ACM Computing Surveys (CSUR), v.32 n.2, p.174-199, June 2000
Rodric M. Rabbah , Krishna V. Palem, Data remapping for design space optimization of embedded memory systems, ACM Transactions on Embedded Computing Systems (TECS), v.2 n.2, p.186-218, May 2003
 
Alexander Gendler , Avi Mendelson , Yitzhak Birk, A PAB-based multi-prefetcher mechanism, International Journal of Parallel Programming, v.34 n.2, p.171-188, April 2006
 
Nikolas Askitis , Ranjan Sinha, HAT-trie: a cache-conscious trie-based data structure for strings, Proceedings of the thirtieth Australasian conference on Computer science, p.97-105, January 30-February 02, 2007, Ballarat, Victoria, Australia

INDEX TERMS

Primary Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
      B.5.1 Design
          Subjects: Memory design

Additional Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories


General Terms:
Design, Performance

Collaborative Colleagues:
John W. C. Fu: colleagues
Janak H. Patel: colleagues
Bob L. Janssens: colleagues

Peer to Peer - Readers of this Article have also read:
This Article has also been published in:

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