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An efficient architecture for loop based data preloading
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Source International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents
Portland, Oregon, United States
Pages: 92 - 101  
Year of Publication: 1992
ISBN:0-8186-3175-9
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Authors
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
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Downloads (6 Weeks): 2,   Downloads (12 Months): 9,   Citation Count: 9
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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M. Wolfe, "Iteration space tiling for memory hierarchies," in Proc. of the 4th SIAM Conference, 1989.
 
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W. Y Chen, S. A. Mahlke, and W. W. Hwu, "Tolerating first level memory access latency in high-performance systems," in Proc. 21th int'l Con}. on Parallel Processing, Aug. 1992.
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CITED BY  9
 
 
 

Collaborative Colleagues:
William Y. Chen: colleagues
Roger A. Bringmann: colleagues
Scott A. Mahlke: colleagues
Richard E. Hank: colleagues
James E. Sicolo: colleagues

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