An efficient architecture for loop based data preloading

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An efficient architecture for loop based data preloading

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International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents

Portland, Oregon, United States

Pages: 92 - 101

Year of Publication: 1992

ISBN:0-8186-3175-9

Also published in ...

Authors

William Y. Chen
Roger A. Bringmann
Scott A. Mahlke
Richard E. Hank
James E. Sicolo

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 9, Citation Count: 9

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Edward H. Gornish , Elana D. Granston , Alexander V. Veidenbaum, Compiler-directed data prefetching in multiprocessors with memory hierarchies, Proceedings of the 4th international conference on Supercomputing, p.354-368, June 11-15, 1990, Amsterdam, The Netherlands
	2	David Callahan , Ken Kennedy , Allan Porterfield, Software prefetching, Proceedings of the fourth international conference on Architectural support for programming languages and operating systems, p.40-52, April 08-11, 1991, Santa Clara, California, United States
	3	Alexander C. Klaiber , Henry M. Levy, An architecture for software-controlled data prefetching, Proceedings of the 18th annual international symposium on Computer architecture, p.43-53, May 27-30, 1991, Toronto, Ontario, Canada
	4	Todd Mowry , Anoop Gupta, Tolerating latency through software-controlled prefetching in shared-memory multiprocessors, Journal of Parallel and Distributed Computing, v.12 n.2, p.87-106, June 1991 [doi>10.1016/0743-7315(91)90014-Z]
	5	William Y. Chen , Scott A. Mahlke , Pohua P. Chang , Wen-mei W. Hwu, Data access microarchitectures for superscalar processors with compiler-assisted data prefetching, Proceedings of the 24th annual international symposium on Microarchitecture, p.69-73, September 1991, Albuquerque, New Mexico, Puerto Rico [doi>10.1145/123465.123478]
	6	M. Wolfe, "Iteration space tiling for memory hierarchies," in Proc. of the 4th SIAM Conference, 1989.
	7	Dennis Gannon , William Jalby , Kyle Gallivan, Strategies for cache and local memory management by global program transformation, Journal of Parallel and Distributed Computing, v.5 n.5, p.587-616, October 1988 [doi>10.1016/0743-7315(88)90014-7]
	8	John W. C. Fu , Janak H. Patel, Data prefetching in multiprocessor vector cache memories, Proceedings of the 18th annual international symposium on Computer architecture, p.54-63, May 27-30, 1991, Toronto, Ontario, Canada
	9	Jean-Loup Baer , Tien-Fu Chen, An effective on-chip preloading scheme to reduce data access penalty, Proceedings of the 1991 ACM/IEEE conference on Supercomputing, p.176-186, November 18-22, 1991, Albuquerque, New Mexico, United States [doi>10.1145/125826.125932]
	10	W. Y Chen, S. A. Mahlke, and W. W. Hwu, "Tolerating first level memory access latency in high-performance systems," in Proc. 21th int'l Con}. on Parallel Processing, Aug. 1992.
	11	Pohua P. Chang , Scott A. Mahlke , William Y. Chen , Nancy J. Warter , Wen-mei W. Hwu, IMPACT: an architectural framework for multiple-instruction-issue processors, Proceedings of the 18th annual international symposium on Computer architecture, p.266-275, May 27-30, 1991, Toronto, Ontario, Canada

CITED BY 9

	Tzi-cker Chiueh, Sunder: a programmable hardware prefetch architecture for numerical loops, Proceedings of the 1994 ACM/IEEE conference on Supercomputing, November 14-18, 1994, Washington, D.C.
	Tzi-Cker Chiueh, Sunder: a programmable hardware prefetch architecture for numerical loops, Proceedings of the 1994 conference on Supercomputing, p.488-497, December 1994, Washington, D.C., United States
	Chi-Hung Chi , Chin-Ming Cheung, Hardware-driven prefetching for pointer data references, Proceedings of the 12th international conference on Supercomputing, p.377-384, July 1998, Melbourne, Australia
	Dorit Naishlos , Marina Biberstein , Shay Ben-David , Ayal Zaks, Vectorizing for a SIMdD DSP architecture, Proceedings of the 2003 international conference on Compilers, architecture and synthesis for embedded systems, October 30-November 01, 2003, San Jose, California, USA
	Jung-Hoon Lee , Shin-Dug Kim , Charles Weems, Application-adaptive intelligent cache memory system, ACM Transactions on Embedded Computing Systems (TECS), v.1 n.1, p.56-78, November 2002
	Dean M. Tullsen , Susan J. Eggers, Effective cache prefetching on bus-based multiprocessors, ACM Transactions on Computer Systems (TOCS), v.13 n.1, p.57-88, Feb. 1995
	Jin-Ho Lee , Min-Young Lee , Seong-Uk Choi , Myong-Soon Park, Reducing cache conflicts in data cache prefetching, ACM SIGARCH Computer Architecture News, v.22 n.4, p.71-77, Sept. 1994
	Sally A. McKee , William A. Wulf , James H. Aylor , Maximo H. Salinas , Robert H. Klenke , Sung I. Hong , Dee A. B. Weikle, Dynamic Access Ordering for Streamed Computations, IEEE Transactions on Computers, v.49 n.11, p.1255-1271, November 2000
	Edward H. Gornish , Alexander Veidenbaum, An Integrated Hardware/Software Data Prefetching Scheme for Shared-Memory Multiprocessors, International Journal of Parallel Programming, v.27 n.1, p.35-70, Feb. 1999

INDEX TERMS

Primary Classification:
B. Hardware
B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
B.1.4 Microprogram Design Aids
Subjects: Languages and compilers

General Terms:
Design, Languages, Performance

Collaborative Colleagues:

William Y. Chen: colleagues

Roger A. Bringmann: colleagues

Scott A. Mahlke: colleagues

Richard E. Hank: colleagues

James E. Sicolo: colleagues

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This Article has also been published in:

ACM SIGMICRO Newsletter
Volume 23 , Issue 1-2 Dec. 1992

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