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Executing compressed programs on an embedded RISC architecture
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Source International Symposium on Microarchitecture archive
Proceedings of the 25th annual international symposium on Microarchitecture table of contents
Portland, Oregon, United States
Pages: 81 - 91  
Year of Publication: 1992
ISBN:0-8186-3175-9
Also published in ...
Authors
Andrew Wolfe
Alex Chanin
Sponsors
IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing
Publisher
IEEE Computer Society Press  Los Alamitos, CA, USA
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Downloads (6 Weeks): 14,   Downloads (12 Months): 75,   Citation Count: 82
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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Chang Hong Lin , Yuan Xie , Wayne Wolf, Code compression for VLIW embedded systems using a self-generating table, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.10, p.1160-1171, October 2007
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Darko Kirovski , Johnson Kin , William H. Mangione-Smith, Procedure based program compression, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.204-213, December 01-03, 1997, Research Triangle Park, North Carolina, United States
X. H. Xu , C. T. Clarke , S. R. Jones, High performance code compression architecture for the embedded ARM/THUMB processor, Proceedings of the 1st conference on Computing frontiers, April 14-16, 2004, Ischia, Italy
 
Darko Kirovski , Johnson Kin , William H. Mangione-Smith, Procedure Based Program Compression, International Journal of Parallel Programming, v.27 n.6, p.457-475, 1999
Haris Lekatsas , Jörg Henkel , Wayne Wolf, Design and simulation of a pipelined decompression architecture for embedded systems, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
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Haris Lekatsas , Jörg Henkel , Wayne Wolf, Code compression as a variable in hardware/software co-design, Proceedings of the eighth international workshop on Hardware/software codesign, p.120-124, May 2000, San Diego, California, United States
 
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Haris Lekatsas , Jörg Henkel , Venkata Jakkula, Design of an one-cycle decompression hardware for performance increase in embedded systems, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
 
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E. Billo , R. Azevedo , G. Araujo , P. Centoducatte , E. Wanderley Netto, Design of a decompressor engine on a SPARC processor, Proceedings of the 18th annual symposium on Integrated circuits and system design, September 04-07, 2005, Florianolpolis, Brazil
Stefan Schaeckeler , Weijia Shang, Stack size reduction of recursive programs, Proceedings of the 2007 international conference on Compilers, architecture, and synthesis for embedded systems, September 30-October 03, 2007, Salzburg, Austria
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Haris Lekatsas , Wayne Wolf, Code compression for embedded systems, Proceedings of the 35th annual conference on Design automation, p.516-521, June 15-19, 1998, San Francisco, California, United States
 
Subash Chandar G , Mahesh Mehendale , R. Govindarajan, Area and power reduction of embedded DSP systems using instruction compression and re-configurable encoding, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
 
Charles Lefurgy , Peter Bird , I-Cheng Chen , Trevor Mudge, Improving code density using compression techniques, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.194-203, December 01-03, 1997, Research Triangle Park, North Carolina, United States
 
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Ramon Canal , Antonio González , James E. Smith, Very low power pipelines using significance compression, Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture, p.181-190, December 2000, Monterey, California, United States
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Heidi Pan , Krste Asanović, Heads and tails: a variable-length instruction format supporting parallel fetch and decode, Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems, November 16-17, 2001, Atlanta, Georgia, USA
 
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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.1 Single Data Stream Architectures
          Subjects: Pipeline processors**

  E. Data
  E.4 CODING AND INFORMATION THEORY
      Subjects: Data compaction and compression


General Terms:
Design, Experimentation, Performance

Collaborative Colleagues:
Andrew Wolfe: colleagues
Alex Chanin: colleagues

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