Investigating the effects of fine-grain three-dimensional integration on microarchitecture design

ABSTRACT

In this article we propose techniques that enable efficient exploration of the 3D design space, where each logical block can span more than one silicon layer. Fine-grain 3D integration provides reduced intrablock wire delay as well as improved power consumption. However, the corresponding power and performance advantage is usually underutilized, since various implementations of multilayer blocks require novel physical design and microarchitecture infrastructure to explore 3D microarchitecture design space. We develop a cubic packing engine which can simultaneously optimize physical and architectural design for efficient vertical integration. This technique selects the individual unit designs from a set of single-layer or multilayer implementations to get the best microarchitectural design in terms of performance, temperature, or both. Our experimental results using a design driver of a high-performance superscalar processor show a 36% performance improvement over traditional 2D for 2--4 layers and 14% over 3D with single-layer unit implementations. Since thermal characteristics of 3D integrated circuits are among the main challenges, thermal-aware floorplanning and thermal via insertion techniques are employed to keep the peak temperatures below threshold.

REFERENCES

• 1: Banerjee, K., Souri, S., Kapur, P., and Saraswat, K. 2001. 3D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration. Proc. IEEE 89, 5, 602--633.
• 2: Bryan Black , Murali Annavaram , Ned Brekelbaum , John DeVale , Lei Jiang , Gabriel H. Loh , Don McCaule , Pat Morrow , Donald W. Nelson , Daniel Pantuso , Paul Reed , Jeff Rupley , Sadasivan Shankar , John Shen , Clair Webb, Die Stacking (3D) Microarchitecture, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.469-479, December 09-13, 2006 [doi>10.1109/MICRO.2006.18]
• 3: Bryan Black , Donald W. Nelson , Clair Webb , Nick Samra, 3D Processing Technology and Its Impact on iA32 Microprocessors, Proceedings of the IEEE International Conference on Computer Design, p.316-318, October 11-13, 2004
• 4: Eric Borch , Srilatha Manne , Joel Emer , Eric Tune, Loose Loops Sink Chips, Proceedings of the 8th International Symposium on High-Performance Computer Architecture, p.299, February 02-06, 2002
• 5: Burger, D. C. and Austin, T. M. 1997. The SimpleScalar tool set. Tech. Rep. CS-TR-97-1342, University of Wisconsin, Madison, Wisconsin. June.
• 6: Burns, J. A., Chen, C. K., Knect, J. M., and Wyatt, P. W. 2006. A wafer-scale 3-D circuit integration technology. IEEE Trans. Electron. Dev. 53, 10, 2507--2516.
• 7: Burns, J., McLlrath, L., Keast, C., Lewis, C., Loomis, A., Warner, K., and Wyatt, P. 2001. Three dimensional integration for low power, high-bandwidth systems on a chip. In Proceedings of the IEEE International Solid State Circuits Conference, San Francisco, CA, 268--269
• 8: Cao, Y., Sato, T., Sylvester, D., Orshansky, M., and Hu, C. 2000. New paradigm of predictive MOSFET and interconnect modeling for early circuit design. In Proceedings of the Custom Integrated Circuit Conference, 201--204.
• 9: Jason Cong , David Zhigang Pan, Interconnect estimation and planning for deep submicron designs, Proceedings of the 36th ACM/IEEE conference on Design automation, p.507-510, June 21-25, 1999, New Orleans, Louisiana, United States [doi>10.1145/309847.309988]
• 10: Jason Cong , Yan Zhang, Thermal-driven multilevel routing for 3-D ICs, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120787]
• 11: Jason Cong , Ashok Jagannathan , Yuchun Ma , Glenn Reinman , Jie Wei , Yan Zhang, An automated design flow for 3D microarchitecture evaluation, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan [doi>10.1145/1118299.1118395]
• 12: J. Cong , Jie Wei , Yan Zhang, A thermal-driven floorplanning algorithm for 3D ICs, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.306-313, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382591]
• 13: Shamik Das , Andy Fan , Kuan-Neng Chen , Chuan Seng Tan , Nisha Checka , Rafael Reif, Technology, performance, and computer-aided design of three-dimensional integrated circuits, Proceedings of the 2004 international symposium on Physical design, April 18-21, 2004, Phoenix, Arizona, USA [doi>10.1145/981066.981091]
• 14: Shamik Das , Anantha Chandrakasan , Rafael Reif, Design tools for 3-D integrated circuits, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan [doi>10.1145/1119772.1119783]
• 15: Keith I. Farkas , Paul Chow , Norman P. Jouppi, Register File Design Considerations in Dynamically Scheduled Processors, Proceedings of the 2nd IEEE Symposium on High-Performance Computer Architecture, p.40, February 03-07, 1996
• 16: Daniele Folegnani , Antonio González, Energy-effective issue logic, Proceedings of the 28th annual international symposium on Computer architecture, p.230-239, June 30-July 04, 2001, Göteborg, Sweden
• 17: Xianlong Hong , Gang Huang , Yici Cai , Jiangchun Gu , Sheqin Dong , Chung Kuan Cheng , Jun Gu, Corner block list: an effective and efficient topological representation of non-slicing floorplan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 18: W.-L. Hung , G. M. Link , Yuan Xie , N. Vijaykrishnan , M. J. Irwin, Interconnect and Thermal-aware Floorplanning for 3D Microprocessors, Proceedings of the 7th International Symposium on Quality Electronic Design, p.98-104, March 27-29, 2006 [doi>10.1109/ISQED.2006.77]
• 19: Ashok Jagannathan , Hannah Honghua Yang , Kris Konigsfeld , Dan Milliron , Mosur Mohan , Michail Romesis , Glenn Reinman , Jason Cong, Microarchitecture evaluation with floorplanning and interconnect pipelining, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China [doi>10.1145/1120725.1120879]
• 20: Kleiner, M. B., Kuhn, S. A., Ramm, P., and Weber, W. 1996. Performance and improvement of the memory hierarchy of Risc-systems by application of 3-D technology. IEEE Trans. Comp. Packag. Manufact. Technol. 19, 4, 709--718.
• 21: Kohira, Y., Kodama, C., Fujiyoshi, K., and Takahashi, A. 2006. Evaluation of 3D-packing represnetations for scheduling of dynamically reconfigurable systems. In Proceddings of the IEEE International Symposium on Circuits and Systems, 4--8.
• 22: Feihui Li , Chrysostomos Nicopoulos , Thomas Richardson , Yuan Xie , Vijaykrishnan Narayanan , Mahmut Kandemir, Design and Management of 3D Chip Multiprocessors Using Network-in-Memory, Proceedings of the 33rd annual international symposium on Computer Architecture, p.130-141, June 17-21, 2006
• 23: Zhuoyuan Li , Xianlong Hong , Qiang Zhou , Shan Zeng , Jinian Bian , Hannah Yang , Vijay Pitchumani , Chung-Kuan Cheng, Integrating dynamic thermal via planning with 3D floorplanning algorithm, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA [doi>10.1145/1123008.1123048]
• 24: Liu, Y., Ma, Y., Kursun, E., Cong, J., and Reinman, G. 2007. Fine grain 3D integration for microarchitecture design through cube packing exploration. In Proceedings of the International Conference on Computer Design, 259--266.
• 25: Gabriel H. Loh, 3D-Stacked Memory Architectures for Multi-core Processors, Proceedings of the 35th International Symposium on Computer Architecture, p.453-464, June 21-25, 2008
• 26: Gabriel H. Loh, A modular 3d processor for flexible product design and technology migration, Proceedings of the 2008 conference on Computing frontiers, May 05-07, 2008, Ischia, Italy [doi>10.1145/1366230.1366261]
• 27: Grant McFarland , Michael J. Flynn, Limits of Scaling MOSFETs, Stanford University, Stanford, CA, 1995
• 28: Ma, Y., Hong, X., Cheng, C. K., and Dong, S. 2005. 3D CBL: An efficient algorithm for general 3-dimensional packing problems. In Proceedings of the IEEE the International Midwest Symposium on Circuits and Systems, 1079--1082.
• 29: MIT Lincoln Laboratory. 2006. Mitll low-power FDSOI CMOS Process: Design guide. March.
• 30: Subbarao Palacharla , Norman P. Jouppi , J. E. Smith, Complexity-effective superscalar processors, Proceedings of the 24th annual international symposium on Computer architecture, p.206-218, June 01-04, 1997, Denver, Colorado, United States
• 31: Kiran Puttaswamy , Gabriel H. Loh, Thermal analysis of a 3D die-stacked high-performance microprocessor, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA [doi>10.1145/1127908.1127915]
• 32: Puttaswamy, K. and Loh, G. H. 2006b. The impact of 3-dimensional integration on the design of arithmetic units. In Proceedings of the International Symposium on Circuits and Systems, 4951--4954.
• 33: Kiran Puttaswamy , Gabriel H. Loh, Dynamic instruction schedulers in a 3-dimensional integration technology, Proceedings of the 16th ACM Great Lakes symposium on VLSI, April 30-May 01, 2006, Philadelphia, PA, USA [doi>10.1145/1127908.1127946]
• 34: Kiran Puttaswamyt , Gabriel H. Loh, Scalability of 3D-integrated arithmetic units in high-performance microprocessors, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278636]
• 35: Reinman, G. and Jouppi, N. 2000. Cacti 2.0: An integrated cache timing and power model. Tech. Rep. 2000/7. Palo Alto, Compaq, California. http://www.hpl.hp.com/techreports/Compaq-DEC/WRL-2000-7.pdf.
• 36: Ronnen, R., Mendelson, A., Lai, K., Liu, S.-L., Pollack, F., and Shen, J. P. 2001. Coming challenges in microarchitecture and architecture. Proc. IEEE 89, 3, 325--340.
• 37: Shivakumar, P. and Jouppi, N. 2001. Cacti 3.0: An integrated cache timing, power, and area model. Tech. Rep. Compaq, Palo Alto, California. www.hpl.hp.com/personal/Norman-Jouppi/eacti3.pdf.
• 38: Eric Sprangle , Doug Carmean, Increasing processor performance by implementing deeper pipelines, Proceedings of the 29th annual international symposium on Computer architecture, May 25-29, 2002, Anchorage, Alaska
• 39: A. W. Topol , D. C. La Tulipe, Jr. , L. Shi , D. J. Frank , K. Bernstein , S. E. Steen , A. Kumar , G. U. Singco , A. M. Young , K. W. Guarini , M. Ieong, Three-dimensional integrated circuits, IBM Journal of Research and Development, v.50 n.4/5, p.491-506, July 2006
• 40: Topol, A. W., La Tulipe, D. C., Shi, L., Alam, S. M., Young, A. M., Frank, D. J., Steen, S. E., Vichiconti, J., Posillico, D., Canaperi, D. M., Medd, S., Conti, R. A., Goma, S., Dimilia, D., Wang, C., Deligianni, L., Cobb, M. A., Jenkins, K., Kumar, A., Kwietniak, K. T., Robson, M., Gibson, G. W., D'Emic, C., Nowak, E., Joshi, R., Guarini, K. W., and Ieong, M. 2005. Enabling SOI-based assembly technology for three dimensional integrated circuits. In Proceedings of the IEEE Interconnection Electron Devices Meeting, 352--355.
• 41: M. Tremblay , B. Joy , K. Shin, A three dimensional register file for superscalar processors, Proceedings of the 28th Hawaii International Conference on System Sciences (HICSS'95), p.191, January 04-07, 1995
• 42: Yuh-Fang Tsai , Yuan Xie , N. Vijaykrishnan , Mary Jane Irwin, Three-Dimensional Cache Design Exploration Using 3DCacti, Proceedings of the 2005 International Conference on Computer Design, p.519-524, October 02-05, 2005 [doi>10.1109/ICCD.2005.108]
• 43: Tsui, Y. K., Lee, S. W. R., Wu, J. S., Kim, J. K., and Yuen, M. M. F. 2003. Three-Dimensional packaging for multi-chip module with through-the-silicon via hole. In Proceedings of the Electronics Packaging Technology, 1--7.
• 44: Wilkerson, P., Raman, A., and Turowski, M. 2004. Fast, automated thermal simulation for three-dimensional integrated circuits. In Proceedings of the Conference on Thermal and Thermomechanical Phenomena in Electronic Circuits, 706--713.
• 45: Xie, Y., Loh, G. H., and Black, B. 2007. Processor design in 3D die-stacking technologies. In Proceedings of the IEEE Micro Conference, 31--48.
• 46: Yuan Xie , Gabriel H. Loh , Bryan Black , Kerry Bernstein, Design space exploration for 3D architectures, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.2 n.2, p.65-103, April 2006 [doi>10.1145/1148015.1148016]
• 47: Xue, L., Liu, C., and Tiwari, S. 2001. Multi-Layers with buried structures (MLBS): An approach to three-dimensional integration. In Proceedings of the IEEE International Conference on Silicon on Insulator, 117--118.
• 48: Yamazaki, H., Sakanushi, K., Nakatake, S., and Kajitani, Y. 2000. The 3D-packing by meta data structure and packing heuristics. IEICE Trans. Fundam. E83-A, 4, 639--645.
• 49: Ping-Hung Yuh , Chia-Lin Yang , Yao-Wen Chang , Hsin-Lung Chen, Temporal floorplanning using 3D-subTCG, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, January 27-30, 2004, Yokohama, Japan

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.0 General

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.0 General

General Terms:
Design, Performance

Keywords:
3D integration, 3D packing, microarchitecture, thermal