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PicoServer: Using 3D stacking technology to build energy efficient servers

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ACM Journal on Emerging Technologies in Computing Systems (JETC) archive
Volume 4 , Issue 4 (October 2008) table of contents

Article No. 16

Year of Publication: 2008

ISSN:1550-4832

Authors

Taeho Kgil	University of Michigan, Intel, Ann Arbor, MI
Ali Saidi	University of Michigan, Ann Arbor, MI
Nathan Binkert	HP Labs, Palo Alto, CA
Steve Reinhardt	University of Michigan, AMD, Ann Arbor, MI
Krisztian Flautner	ARM, Cambridge, UK
Trevor Mudge	University of Michigan, Ann Arbor, MI

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ACM New York, NY, USA

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ABSTRACT

This article extends our prior work to show that a straightforward use of 3D stacking technology enables the design of compact energy-efficient servers. Our proposed architecture, called PicoServer, employs 3D technology to bond one die containing several simple, slow processing cores to multiple memory dies sufficient for a primary memory. The multiple memory dies are composed of DRAM. This use of 3D stacks readily facilitates wide low-latency buses between processors and memory. These remove the need for an L2 cache allowing its area to be re-allocated to additional simple cores. The additional cores allow the clock frequency to be lowered without impairing throughput. Lower clock frequency means that thermal constraints, a concern with 3D stacking, are easily satisfied. We extend our original analysis on PicoServer to include: (1) a wider set of server workloads, (2) the impact of multithreading, and (3) the on-chip DRAM architecture and system memory usage. PicoServer is intentionally simple, requiring only the simplest form of 3D technology where die are stacked on top of one another. Our intent is to minimize risk of introducing a new technology (3D) to implement a class of low-cost, low-power compact server architectures.

REFERENCES

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