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A lower bound for sorting networks based on the shuffle permutation
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Source ACM Symposium on Parallel Algorithms and Architectures archive
Proceedings of the fourth annual ACM symposium on Parallel algorithms and architectures table of contents
San Diego, California, United States
Pages: 70 - 79  
Year of Publication: 1992
ISBN:0-89791-483-X
Authors
Sponsors
SIGACT: ACM Special Interest Group on Algorithms and Computation Theory
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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K. E. Batcher. Sorting networks and their applications, in Proceedings of the AFIPS Spring Joint Computer Conference, vo}. 32, pages 307- 314, 1968.
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R. E. Cypher. Theoretical aspects of VLSI pin limitations. Technical Report RJ7115, IBM Almaden Research Center, November 1989.
 
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F. T. Leighton and C. G. Plaxton. A (fairly) simple circuit that (usually) sorts. In Proceedings o/ the 31st Annual IEEE Symposium on Foundations of Computer Science, pages 264-274, October 1990.
 
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M. S. Paterson. Improved sorting networks with O(logn) depth. Algorithmica, 5:75-92, 1990.
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Collaborative Colleagues:
C. Greg Plaxton: colleagues
Torsten Suel: colleagues

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