A simplified executable model to evaluate latency and throughput of networks-on-chip

ABSTRACT

This paper proposes a technique that mixes simulation and an analytical method to evaluate the characteristics of Networks-on-Chips (NoCs). The advantage of this technique is to reduce the simulation time by reducing the complexity of the NoC model while still obtaining accurate results for latency and throughput. The basis of this technique is: (i) to send the whole payload data at once in the packet header; (ii) to reduce the NoC simulation complexity by omitting the flit by flit payload forwarding; (iii) to use an algorithm for controlling the release of the packet trailer in order to close the connection at the right time. For the evaluation of this technique, an actor-oriented model of a NoC, JOSELITO, was created. Simulation results show that JOSELITO is in average 2.3 times faster in 88% of the executed case studies than the implementation without using the proposed technique. The worst case simulation results for latency and throughput have, respectively, 5.26% and 0.1% error compared to the corresponding Register Transfer Level (RTL) model.

REFERENCES

• 1: Partha Pratim Pande , Cristian Grecu , Michael Jones , Andre Ivanov , Resve Saleh, Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures, IEEE Transactions on Computers, v.54 n.8, p.1025-1040, August 2005 [doi>10.1109/TC.2005.134]
• 2: Wayne Wolf, The future of multiprocessor systems-on-chips, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996753]
• 3: Luca Benini , Giovanni De Micheli, Networks on Chips: A New SoC Paradigm, Computer, v.35 n.1, p.70-78, January 2002 [doi>10.1109/2.976921]
• 4: Fernando Moraes , Ney Calazans , Aline Mello , Leandro Möller , Luciano Ost, HERMES: an infrastructure for low area overhead packet-switching networks on chip, Integration, the VLSI Journal, v.38 n.1, p.69-93, October 2004 [doi>10.1016/j.vlsi.2004.03.003]
• 5: Grant Martin, Overview of the MPSoC design challenge, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146980]
• 6: Tobias Bjerregaard , Shankar Mahadevan, A survey of research and practices of Network-on-chip, ACM Computing Surveys (CSUR), v.38 n.1, p.1-es, 2006 [doi>http://doi.acm.org/10.1145/1132952.1132953]
• 7: Davide Bertozzi , Antoine Jalabert , Srinivasan Murali , Rutuparna Tamhankar , Stergios Stergiou , Luca Benini , Giovanni De Micheli, NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip, IEEE Transactions on Parallel and Distributed Systems, v.16 n.2, p.113-129, February 2005 [doi>10.1109/TPDS.2005.22]
• 8: Srinivasan Murali , Giovanni De Micheli, SUNMAP: a tool for automatic topology selection and generation for NoCs, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996809]
• 9: Meloni, P.; Murali, S.; Carta, S.; Camplani, M.; Raffo, L. De Micheli, G. Routing Aware Switch Hardware Customization for Networks on Chips. In: NanoNet, 2006.
• 10: Xu, J.; Wolf, W.; Henkel, J.; Chakradhar, S. A Methodology for Design, Modeling, and Analysis of Network on Chip. In: ISCAS, 2005.
• 11: Tim Kogel , Malte Doerper , Andreas Wieferink , Rainer Leupers , Gerd Ascheid , Heinrich Meyr , Serge Goossens, A modular simulation framework for architectural exploration of on-chip interconnection networks, Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, October 01-03, 2003, Newport Beach, CA, USA [doi>10.1145/944645.944648]
• 12: Marcello Coppola , Stephane Curaba , Miltos D. Grammatikakis , Giuseppe Maruccia , Francesco Papariello, OCCN: A Network-On-Chip Modeling and Simulation Framework, Proceedings of the conference on Design, automation and test in Europe, p.30174, February 16-20, 2004
• 13: Florin Dumitrascu , Iuliana Bacivarov , Lorenzo Pieralisi , Marius Bonaciu , Ahmed A. Jerraya, Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application, Proceedings of the conference on Design, automation and test in Europe: Designers' forum, March 06-10, 2006, Munich, Germany
• 14: Santiago Gonzalez Pestana , Edwin Rijpkema , Andrei Rdulescu , Kees Goossens , Om Prakash Gangwal, Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach, Proceedings of the conference on Design, automation and test in Europe, p.20764, February 16-20, 2004
• 15: Leandro Soares Indrusiak , Luciano Ost , Leandro Möller , Fernando Moraes , Manfred Glesner, Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects, Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI, p.491-494, April 07-09, 2008 [doi>10.1109/ISVLSI.2008.20]
• 16: Liu, J; Eker, J; Janneck, J W.; Liu, X J. and Lee, E A. Actor-oriented control system design: A responsible framework perspective. IEEE Transactions on Control Systems Technology, 12(2), 2004.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design, Experimentation, Performance, Verification

Keywords:
modeling, networks-on-chip, performance evaluation