ACM Home Page
Please provide us with feedback. Feedback
Encountering gate oxide breakdown with shadow transistors to increase reliability
Full text PdfPdf (413 KB)
Source
SBCCI archive
Proceedings of the 21st annual symposium on Integrated circuits and system design table of contents
Gramado, Brazil
SESSION: Design for reliability table of contents
Pages 111-116  
Year of Publication: 2008
ISBN:978-1-60558-231-3
Authors
Claas Cornelius  University of Rostock, Rostock, Germany
Frank Sill  Federal University of Minas Gerais, Belo Horizonte, Brazil
Hagen Sämrow  University of Rostock, Rostock, Germany
Jakob Salzmann  University of Rostock, Rostock, Germany
Dirk Timmermann  University of Rostock, Rostock, Germany
Diógenes da Silva  Federal University of Minas Gerais, Belo Horizonte, Brazil
Sponsors
ACM: Association for Computing Machinery
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 3,   Downloads (12 Months): 33,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1404371.1404407
What is a DOI?

ABSTRACT

Device scaling has enabled continuous performance increase of integrated circuits. However, severe reliability and yield concerns are arising against the background of nanotechnology. Tradition-ally, most causes and countermeasures were solely considered manufacturing issues, but lately, we have seen a shift towards op-erational reliability issues. Though, besides intense research on soft-errors and system-level approaches very little effort is put into low-level design solutions in order to enhance lifetime reliability. Hence, we demonstrate that redundant transistor insertion does im-prove system reliability significantly as regards Time-Dependent Dielectric Breakdown (TDDB). Furthermore, we introduce an al-gorithm which identifies the transistors being most vulnerable to TDDB. Subsequently, redundant transistors (called shadow transis-tors) are inserted at the previously identified instances. Lastly, we argue for applying high threshold voltage devices for the redundant transistors. Finally, we present results for a set of benchmark cir-cuits and prove the combined approach successful. The enhanced designs were on average 41.8% more reliable compared to the ini-tial designs in respect of TDDB at the price of moderately in-creased power consumption and delay.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
Chiluvuri, V. and Koren, I. "Layout-Synthesis Techniques for Yield Enhancement", In Trans. of Semiconductor Manufacturing, vol. 8, no. 2, 1995.
 
3
Cornelius, C., Sill, F. and Timmermann, D., "Modeling the Power-Reliability Tradeoff in On-Chip Networks", In Proc. of Symposium Maritime Elektrotechnik, 2007.
 
4
Crook, D., "Method of Determining Reliability Screens for Time Dependent Reliability Breakdown", In Proc. of Intern. Reliability Physics Symposium, 1979.
 
5
 
6
Degraeve, R., Kaczer, B., De Keersgieter, A. and Groeseneken, G., "Relation between Breakdown Mode and Breakdown Location in Short Channel nMOSFETs and its Impact on Reliability Specifications", In Proc. of IRPS,2001.
 
7
 
8
 
9
 
10
 
11
Reichenbach, F., Bobek, A., Hagen, P., Timmermann, D., "Increasing Lifetime of Wireless Sensor Networks with Energy-Aware Role-Changing", In Proc. of SelfMan, 2006.
 
12
 
13
 
14
 
15
Semiconductor Industry Association (SIA), "International Technology Roadmap for Semiconductors", Release 2007, Published on-line: http://www.itrs.net/.
16
 
17
 
18
Srinivasan, J. et al., "RAMP: A Model for Reliability Aware Microprocessor Design", In IBM Research Report, RC23048, 2003.
 
19
 
20
Stathis, J., "Reliability Limits for the Gate Insulator in CMOS Technology", In IBM Journal of Research and Development, 2002.
 
21
 
22
Tschanz, J. et al., "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage", In JSSC, vol. 37, 2002.
 
23
Vogel, E. et al., "Reliability of Ultra-Thin Silicon Dioxide Under Combined Substrate Hot Electron and Constant Voltage Tunneling Stress", In Trans. of Electron Devices, vol. 47, no. 6, 2000.
 
24
Wu, E. and Sune, J., "Power-Law Voltage Acceleration: A Key Element for Ultra-thin Gate Oxide Reliability", In Microelectronics Reliability, 2005.

Collaborative Colleagues:
Claas Cornelius: colleagues
Frank Sill: colleagues
Hagen Sämrow: colleagues
Jakob Salzmann: colleagues
Dirk Timmermann: colleagues
Diógenes da Silva: colleagues