ABSTRACT
As IC fabrication technology continues its evolution, scaling down into nanometer dimensions, new challenges and opportunities arise for the semiconductor industry. Current device integration supports the development of highly complex systems on a chip, including digital, analog, and RF technologies. Several defying issues surface, starting at system level, where new methodologies and EDA tools must be developed to deal with the integration of heterogeneous technologies and system complexity, down to the technology level, where device models no longer rely on deterministic behavior: most relevant parameters are statistical, with subtle interactions. Power consumption not only concerns portable devices but also supercomputers, which must reduce its huge electrical bill. The test community faces new challenges, as nanodevices introduce new kinds of errors, such as an increasing sensibility to terrestrial radiations, soft errors, increasing leakage problems, and so on. Moreover, time-to-market for new electronic products is steadily decreasing, adding more pressure to the semiconductor community. This panel aims to discuss the main challenges introduced by the nanoscale era and provide some insights into future research directions.
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B.7