Instruction-driven clock scheduling with glitch mitigation

ABSTRACT

Instruction-driven clock scheduling is a mechanism that minimizes clock power in deeply-pipelined datapaths. Analysis of realistic processor workloads shows a preponderance of bubbles persist through pipelines like the floating point unit. Clock scheduling ostensibly adapts pipeline depth with respect to bubbles in the instruction stream without performance loss. Unfortunately, shallower pipelines (i.e. longer pipe stages) are prone to larger amounts of glitches propagating through logic, increasing dynamic power. Experimentally measured results from a 130nm FPU test chip with flexible clocking capabilities show a super-linear increase in glitch-induced dynamic power for shallower pipelines. While higher glitch power can severely diminish the power savings offered by clock scheduling, judicious clocking of intermediate stages offers glitch mitigation to recover power savings for worst-case scenarios. Detailed analysis of clock scheduling applied to a FPU in a POWER4-like processor running realistic workloads shows an average net power savings of 15% compared to an aggressively clock-gated design.

REFERENCES

• 1: Shekhar Borkar, Thousand core chips: a technology perspective, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California [doi>10.1145/1278480.1278667]
• 2: Hans M. Jacobson, Improved clock-gating through transparent pipelining, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA [doi>10.1145/1013235.1013248]
• 3: D. Brooks , P. Bose , V. Srinivasan , M. K. Gschwind , P. G. Emma , M. G. Rosenfield, New methodology for early-stage, microarchitecture-level power-performance analysis of microprocessors, IBM Journal of Research and Development, v.47 n.5-6, p.653-670, September 2003
• 4: Mayan Moudgill , John-David Wellman , Jaime H. Moreno, Environment for PowerPC Microarchitecture Exploration, IEEE Micro, v.19 n.3, p.15-25, May 1999 [doi>10.1109/40.768496]
• 5: David M. Brooks , Pradip Bose , Stanley E. Schuster , Hans Jacobson , Prabhakar N. Kudva , Alper Buyuktosunoglu , John-David Wellman , Victor Zyuban , Manish Gupta , Peter W. Cook, Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors, IEEE Micro, v.20 n.6, p.26-44, November 2000 [doi>10.1109/40.888701]
• 6: X. Liang, D. Brooks, and G.-Y. Wei, "A process variation tolerant floating-point unit with voltage interpolation and variable latency," in Proc. IEEE International Solid-State Circuits Conference, Feb. 2008.
• 7: Hans Jacobson , Pradip Bose , Zhigang Hu , Alper Buyuktosunoglu , Victor Zyuban , Rick Eickemeyer , Lee Eisen , John Griswell , Doug Logan , Balaram Sinharoy , Joel Tendler, Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors, Proceedings of the 11th International Symposium on High-Performance Computer Architecture, p.238-242, February 12-16, 2005 [doi>10.1109/HPCA.2005.33]
• 8: Eric L. Hill , Mikko H. Lipasti, Stall cycle redistribution in a transparent fetch pipeline, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany [doi>10.1145/1165573.1165583]

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization
  C.4 PERFORMANCE OF SYSTEMS
      Subjects: Design studies

General Terms:
Design

Keywords:
clock gating, floating point unit, glitch power, low power