Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion

ABSTRACT

A simple yet effective technique that aims at reducing the energy and latency overheads incurred during the wakeup period of MTCMOS circuits is presented in this paper. One or more high-V_th keepers are inserted in MTCMOS combinational logic to reduce the metastability time that causes excessive short circuit current during mode transition and to minimize spurious glitches at internal circuit nodes. Employing the proposed keeper insertion technique in a 16-bit MTCMOS adder, up to 17.5% average wakeup energy and 54.6% wakeup latency reductions are achieved with negligible runtime power and latency overheads, while maintaining the standby energy efficiency of the original MTCMOS design.

REFERENCES

• 1: Tanay Karnik , Shekhar Borkar , Vivek De, Sub-90nm technologies: challenges and opportunities for CAD, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.203-206, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774602]
• 2: Lawrence T. Clark , Michael Morrow , William Brown, Reverse-body bias and supply collapse for low effective standby power, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.9, p.947-956, September 2004 [doi>10.1109/TVLSI.2004.832930]
• 3: S. Mutoh et al., "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," IEEE J. Solid-State Circuits, vol. 30, pp. 847--854, Aug. 1995.
• 4: M. Anis, S. Areibi, and M. Elmasry, "Design and optimization of multithreshold CMOS (MTCMOS) circuits," IEEE Trans. CAD of Integ. Circuits and Syst., vol. 22, no. 10, pp. 1324--1342, Oct. 2003.
• 5: James Kao , Anantha Chandrakasan , Dimitri Antoniadis, Transistor sizing issues and tool for multi-threshold CMOS technology, Proceedings of the 34th annual conference on Design automation, p.409-414, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266182]
• 6: Z. Liu, and V. Kursun, "Leakage biased pmos sleep switch dynamic circuits," IEEE Trans. Circuits and Syst. II, vol. 53, no. 10, Oct. 2006.
• 7: Ehsan Pakbaznia , Farzan Fallah , Massoud Pedram, Charge recycling in MTCMOS circuits: concept and analysis, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA [doi>10.1145/1146909.1146940]
• 8: Suhwan Kim , Stephen V. Kosonocky , Daniel R. Knebel, Understanding and minimizing ground bounce during mode transition of power gating structures, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea [doi>10.1145/871506.871515]
• 9: A. Abdollahi, F. Fallah, and M. Pedram, "A robust power gating structure and power mode transition strategy for MTCMOS design," IEEE Trans. VLSI Syst., vol. 15, no. 1, pp. 80--89, Jan. 2007.
• 10: Yu-Ting Chen , Da-Cheng Juan , Ming-Chao Lee , Shih-Chieh Chang, An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon, Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, November 05-08, 2007, San Jose, California

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design, Performance, Reliability

Keywords:
leakage power, mode transition, power gating