Post-silicon programmed body-biasing platform suppressing device variability in 45 nm CMOS technology

ABSTRACT

The Post-Silicon Programmed Body-Biasing Platform is proposed to suppress device variability in the 45-nm CMOS technology era. The proposed platform measures device speed during post-fabrication testing. Then the fast die is marked so that the body-bias circuit turns on and reduces leakage current of the die that is selected and marked in a user application. Because the slow die around the speed specifications of a product is not body-biased, the product runs as fast as a normal non-body-biasing product. Although the leakage power of a fast die is reduced, the speed specification does not change. The proposed platform improves the worst corner specification comprising the two worst cases of speed and leakage power. The test chip, fabricated using 45-nm technology, improves the worst corner of stand-by leakage power vs. speed by 70%.

REFERENCES

• 1: J. Tschanz, et al., "Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging," ISSCC, pp. 292--293, 2007.
• 2: M. Nomura, et al., "Monitoring Scheme for Minimizing Power Consumption by Means of Supply and Threshold Voltage Control in Active and Standby Modes," Symp. VLSI Circuits, pp. 308--311, 2005.
• 3: M. Sumita, et al., "Mixed Body-Bias Techniques with Fixed Vt and Ids Generation Circuits," ISSCC, pp. 233--234, 2004.
• 4: J. Tschanz, et al., "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," ISSCC, pp. 422--423, 2002.
• 5: M. Miyazaki, et al., "A 1000-MIPS/W Microprocessor using Speed-Adaptive Threshold-Voltage CMOS with Forward Bias," ISSCC, pp. 420--421, 2000.

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: Advanced technologies

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

General Terms:
Design, Experimentation, Measurement, Performance

Keywords:
body-biasing, device variability suppression, leakage current reduction, post-silicon programming