The mixed signal optimum energy point

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The mixed signal optimum energy point: voltage and parallelism

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 45th annual Design Automation Conference table of contents

Anaheim, California

SESSION: Multi-core simulation, mixed-signal power optimization and nanodevices table of contents

Pages 244-249

Year of Publication: 2008

ISBN ~ ISSN:0738-100X , 978-1-60558-115-6

Authors

Brian P. Ginsburg	Texas Instruments, Dallas, TX
Anantha P. Chandrakasan	Massachusetts Institute of Technology, Cambridge, MA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
: IEEE/CASS/CANDE/CEDA
: The EDA Consortium

Publisher

ACM New York, NY, USA

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ABSTRACT

An energy optimization is proposed that addresses the non-trivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and behavioral models are used to quantify architectural tradeoffs across the analog/digital boundary. An interleaved ADC is optimized as a case study to demonstrate this approach. The chosen operating point of 36 channels and 700mV operation gives a 3× improvement in energy compared to the seed of the model. The model matches closely the measured results of an ADC testchip implemented in a 65nm CMOS process.

REFERENCES

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	1	J. Goes, J. Vital, and J. Franca, "Systematic design for optimization of high-speed self-calibrated pipelined A/D converters." IEEE Trans. Circuits Syst. II, vol. 45, no. 12, pp. 1513--1526, Dec. 1998.
	2	Y. Lin et al., "kT/C constrained optimization of power in pipeline ADCs," in Proc. of the IEEE Int. Symp. on Circuits and Systems, vol. 3, May 2005, pp. 1968--1971.
	3	Maria del Mar Hershenson, Design of pipeline analog-to-digital converters via geometric programming, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.317-324, November 10-14, 2002, San Jose, California [doi>10.1145/774572.774620]
	4	A. Chandrakasan, S. Sheng, and R. Brodersen, "Low-power CMOS digital design," IEEE J. Solid-State Circuits, vol. 27, no. 4, pp. 473--484, Apr 1992.
	5	D. Markovic et al., "Methods for true energy-performance optimization," IEEE J. Solid-State Circuits, vol. 39, no. 8, pp. 1282--1293, Aug. 2004.
	6	Victor Zyuban , Philip Strenski, Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566451]
	7	D. Draxelmayr, "A 6b 600MHz 10mW ADC array in digital 90nm CMOS," in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 264--265.
	8	B. P. Ginsburg and A. P. Chandrakasan, "Dual time-interleaved successive approximation register ADCs for an ultra-wideband receiver," IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 247--257, Feb. 2007.
	9	B. P. Ginsburg, "500-MS/s 5-b ADC in 65-nm CMOS with split capacitor array DAC," IEEE J. Solid-State Circuits, vol. 42, pp. 739--747, Apr. 2007.
	10	S.-W. M. Chen and R. W. Brodersen, "A 6b 600MS/s 5.3mW asynchronous ADC in 0.13μm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers, vol. 49, Feb. 2006, pp. 574--575.
	11	P. P. Newaskar, R. Blazquez, and A. P. Chandrakasan, "A/D precision requirements for an ultra-wideband radio receiver," in IEEE Workshop on Signal Processing Systems, Oct. 2002, pp. 270--275.
	12	B. P. Ginsburg, "Energy-efficient analog-to-digital conversion for ultra-wideband radio," Ph.D. dissertation, Massachusetts Institute of Technology, Cambridge, MA, 2007.
	13	S. Gambini and J. Rabaey, "Low-power successive approximation converter with 0.5 V supply in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2348--2356, Nov. 2007.
	14	T. Brooks et al., "A cascaded sigma-delta pipeline A/D converter with 1.25 MHz signal bandwidth and 89 dB SNR," IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1896--1906, Dec. 1997.
	15	G.-C. Ahn et al., "A 0.6-V 82-dB delta-sigma audio ADC using switched-RC integrators," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2398--2407, Dec. 2005.
	16	D. Fu et al., "A digital background calibration technique for time-interleaved analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1904--1911, Dec. 1998.
	17	J. M. Rabaey, A. Chandrakasan, and B. Nikolić, Digital Integrated Circuits, 2nd ed. Prentice-Hall, 2002.
	18	D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 663--670, Jun. 1994.
	19	B. P. Ginsburg and A. P. Chandrakasan, "Highly-interleaved 5b 250MS/s ADC with redundant channels in 65nm CMOS," in IEEE Int. Solid-State Circuits Conf. Dig. of Tech. Papers, vol. 51, Feb. 2008, pp. 240--241.