ACM Home Page
Please provide us with feedback. Feedback
Analysis of dynamic power management on multi-core processors
Full text PdfPdf (766 KB)
Source
International Conference on Supercomputing archive
Proceedings of the 22nd annual international conference on Supercomputing table of contents
Island of Kos, Greece
SESSION: Architecture 2 table of contents
Pages 327-338  
Year of Publication: 2008
ISBN:978-1-60558-158-3
Authors
W. Lloyd Bircher  The University of Texas at Austin, Austin, TX, USA
Lizy K. John  The University of Texas at Austin, Austin, TX, USA
Sponsors
ACM: Association for Computing Machinery
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 27,   Downloads (12 Months): 329,   Citation Count: 0
Additional Information:

abstract   references   index terms   collaborative colleagues  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/1375527.1375575
What is a DOI?

ABSTRACT

Power management of multi-core processors is extremely important because it allows power/energy savings when all cores are not used. OS directed power management according to ACPI (Advanced Power and Configurations Interface) specifications is the common approach that industry has adopted for this purpose. While operating systems are capable of such power management, heuristics for effectively managing the power are still evolving. The granularity at which the cores are slowed down/turned off should be designed considering the phase behavior of the workloads. Using 3-D, video creation, office and e-learning applications from the SYSmark benchmark suite, we study the challenges in power management of a multi-core processor such as the AMD Quad-Core Opteron" and Phenom". We unveil effects of the idle core frequency on the performance and power of the active cores. We adjust the idle core frequency to have the least detrimental effect on the active core performance. We present optimized hardware and operating system configurations that reduce average active power by 30% while reducing performance by an average of less than 3%. We also present complete system measurements and power breakdown between the various systems components using the SYSmark and SPEC CPU workloads. It is observed that the processor core and the disk consume the most power, with core having the highest variability.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
Advanced Configuration & Power Interface. http://www.acpi.info. November 2007.
 
2
BIOS and Kernel Developer's Guide for AMD Family 10h Processor. http://www.amd.com. November 2007.
 
3
Bircher, W. L. Measurement Based Power Phase Analysis of a Commercial Workload. Workshop on Unique Chips and Systems (Austin, Texas, March 2006).
4
 
5
Bohrer, P., Elnozahy, E. N., Keller, T., Kistler, M., Lefurgy, C., McDowell, C., and Rajamony, R. The Case for Power Management in Web Servers. IBM Research, Austin TX 78758, USA. www.research.ibm.com/arl
6
 
7
 
8
Hanson, H., Keckler, S.W. Power and Performance Optimization: A Case Study with the Pentium M Processor. The Austin Center for Advanced Studies Conference (February 2006).
 
9
Hanson, H., Keckler, S.W., Rajamani, K., Ghiasi, S., Rawson, F., and Rubio, J. Power, Performance, and Thermal Management for High-Performance Systems. 3rd Workshop on High-Performance, Power-Aware Computing, held in conjunction with 21st Annual International Parallel & Distributed Processing Symposium (Long Beach, California, March 2007).
 
10
 
11
Kotla, R., Devgan, A., Ghiasi, S., Keller, T., and Rawson, F. Characterizing the Impact of Different Memory--Intensity Levels. IEEE 7th Annual Workshop on Workload Characterization (Austin, Texas, October 2004).
 
12
 
13
Li, J. and Martinez, J. Dynamic Power--Performance Adaptation of Parallel Computation on Chip Multiprocessors. The 12th International Symposium on High--Performance Computer Architecture (Austin, Texas, February 2006).
 
14
 
15
Mahesri, A. and Vardhan, V. Power Consumption Breakdown on a Modern Laptop. Workshop on Power Aware Computing Systems, 37th International Symposium on Microarchitecture (Portland, Oregon, December 2004).
 
16
Processor Power Management in Windows Vista and Windows Server 2008. http://www.microsoft.com . November 2007.
 
17
National Instruments Data Acquisition Hardware. http://www.ni.com/dataacquisition/. April 2008.
 
18
Rajamani, K., Hanson, H., Rubio, J., Ghiasi, S., and Rawson, F. Application-Aware Power Management. IEEE International Symposium on Workload Characterization pages 39--48 (San Jose, California, October 2006).
 
19
Inside Barcelona: AMD's Next Generation http://www.realworldtech.com . November 2007.
 
20
Siddah, S., Pallipadi, V., and Van de Ven, A. Getting Maximum Mileage Out of Tickless. The Linux Symposium. (Ottawa, Canada, June 2007).

Collaborative Colleagues:
W. Lloyd Bircher: colleagues
Lizy K. John: colleagues