| Mesh-of-tree deterministic routing for network-on-chip architecture |
| Full text |
Pdf
(282 KB)
|
Source
|
Great Lakes Symposium on VLSI
archive
Proceedings of the 18th ACM Great Lakes symposium on VLSI
table of contents
Orlando, Florida, USA
POSTER SESSION: Poster session 2
table of contents
Pages 343-346
Year of Publication: 2008
ISBN:978-1-59593-999-9
|
|
Authors
|
|
| Sponsors |
|
| Publisher |
|
| Bibliometrics |
Downloads (6 Weeks): 11, Downloads (12 Months): 84, Citation Count: 0
|
|
|
ABSTRACT
Network-on-Chip (NoC) is a new paradigm for designing future SoCs. It supports high degree of reusability, scalability, and parallelism in communication. Here, we present Mesh-of-Tree (MoT) based deterministic routing for NoC architecture. MoT interconnection has the advantage of having small diameter as well as large bisection width. The routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock and livelock free.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
| |
1
|
|
 |
2
|
|
| |
3
|
|
| |
4
|
W. J. Dally et al, "The Torus Routing Chip", Journal of Distributed Computing, pp. 187--196, Oct 1986.
|
| |
5
|
|
 |
6
|
|
| |
7
|
|
| |
8
|
Pande et al., "High-Throughput Switch-based Interconnect for future SoCs", Proc. Third IEEE Int?l Workshop System-on-Chip for real time Applications, pp. 304--310, 2003.
|
| |
9
|
|
| |
10
|
|
| |
11
|
|
| |
12
|
Interconnection Network architectures, Jan 2001, pp. 26--49. www.wellesley.edu/cs/courses/cs331/notes/notesnetworks.pdf
|
| |
13
|
|
 |
14
|
|
| |
15
|
S. Kundu et al., "Interfacing Cores and Routers in Network-on-Chip Using GALS", IEEE International Symposium on Integrated Circuits (ISIC), Singapore, 2007.
|
|