Improved simple simulation models for semiconductor wafer factories

ABSTRACT

Semiconductor wafer fabrication facilities (wafer fabs) are among the most complex production facilities. A large product variety, hundreds of processing steps per product, hundreds of machines of different types, and automated transport lead to a system complexity which is hard to understand and hard to handle. For educating planners and developing adequate material flow control mechanisms, simple models for this complex environment are required. Several years ago, we published some first approaches which were useful to explain the fab behavior after a serious bottleneck breakdown. With that simple model, however, it was only possible to predict the cycle time distribution of the lots for a few scenarios. In this paper, we present some model improvements which lead to a rather good cycle time prediction for a variety of load situations.

REFERENCES

• 1: Oliver Rose, WIP evolution of a semiconductor factory after a bottleneck workcenter breakdown, Proceedings of the 30th conference on Winter simulation, p.997-1004, December 13-16, 1998, Washington, D.C., United States
• 2: Rose, O. 1999a. Estimation of the cycle time distribution of a wafer fab by a simple simulation model. In Proceedings of the 1999 SMOMS (1999 WMC), 133--138.
• 3: Oliver Rose, CONLOAD—a new lot release rule for semiconductor wafer fabs, Proceedings of the 31st conference on Winter simulation: Simulation---a bridge to the future, p.850-855, December 05-08, 1999, Phoenix, Arizona, United States [doi>10.1145/324138.324535]
• 4: Oliver Rose, General simulation applications in semiconductor manufacturing: why do simple wafer fab models fail in certain scenarios?, Proceedings of the 32nd conference on Winter simulation, December 10-13, 2000, Orlando, Florida
• 5: Rose, O. 2007. Improving the accuracy of simple simulation Models for complex production systems. In Proceedings of the 2007 INFORMS Simulation Society Research Workshop, Fontainebleau, July 5-7, 2007.