Providing a laboratory for instruction set design

ABSTRACT

Computer architecture classes do not provide students with laboratory experience in the design of instruction set architectures. Projects that compare designs have not been possible due to a lack of support software. The design and evaluation of a new instruction set requires an assembler, a symbolic debugger, and a statistics gatherer. Every new instruction set requires changes to all three programs. It would be unrealistic to expect that either students or instructor would (re)write such software in order to evaluate each new design. A new, flexible software package called the Instruction Set Testbed (IST) provides for the comparison of instruction set architectures without writing any of the support software. IST's table-driven assembler uses a student-supplied architecture definition to assemble programs. IST's interactive debugger and a statistics gatherer also have access to the architecture definition. This allows symbolic debugging of the assembly language programs and automatic histogramming of instruction usage in the student-defined architecture. IST has been used in both undergraduate and graduate architecture classes to investigate such topics as orthogonality, choice and number of operands, addressing modes, and RISC philosophy.

REFERENCES

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INDEX TERMS

Primary Classification:
  K. Computing Milieux
  K.3 COMPUTERS AND EDUCATION
      K.3.2 Computer and Information Science Education
          Subjects: Computer science education

Additional Classification:
  C. Computer Systems Organization
  C.0 GENERAL
      Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

General Terms:
Design, Human Factors