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ABSTRACT
Current source models have emerged as a promising technique for reducing digital cell netlists to a simpler electrical model for use in timing and other applications. The Multiport Current Source Model (MCSM) is one of the most general models in this class, which has been shown to handle multiple electrical effects including multiple-input switching (MIS) events in timing. However, this new model is hampered by two major problems: port characterization runtime and accuracy across a range of complicated cells which are deployed in advanced microprocessor design such as complex combinational cells, muxes, and sequentials. In this paper we demonstrate a significant leap in modeling accuracy and characterization runtime over the MCSM model which effectively eliminates these remaining issues. The quality of the new approach is conclusively demonstrated on a comprehensive 45nm cell library currently in use. The new approach accurately models both complex combinational as well as, for the first time, sequential cells, and puts MCSMs on the path for next generation gate level electrical analysis.
REFERENCES
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CITED BY 3
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S. Raja , F. Varadi , M. Becer , J. Geada, Transistor level gate modeling for accurate and fast timing, noise, and power analysis, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
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Noel Menezes , Chandramouli Kashyap , Chirayu Amin, A "true" electrical cell model for timing, noise, and power grid verification, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
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