Analog placement with common centroid constraints

ABSTRACT

In order to reduce parasitic mismatch in analog circuits, some groups of devices are required to share a common centroid while being placed. Devices are split into smaller ones and placed with a common center point. We will address this problem of handling common centroid constraint in placement. A new representation called Center-based Corner Block List (C-CBL) is proposed which is a natural extension of Corner Block List (CBL) [1] to represent a common centroid placement of a set of device pairs. C-CBL is complete and non-redundant in representing any common centroid mosaic packings with pairs of blocks to be matched. To address the same problem with an additional constraint that devices are required to be placed uniformly to average out the parasitic errors, a grid-based approach is proposed. Experimental results show that both approaches are fast and promising, and have high scalability that even large data sets can be handled effectively.

REFERENCES

• 1: Xianlong Hong , Gang Huang , Yici Cai , Jiangchun Gu , Sheqin Dong , Chung Kuan Cheng , Jun Gu, Corner block list: an effective and efficient topological representation of non-slicing floorplan, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
• 2: Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani, Rectangle-packing-based module placement, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.472-479, November 05-09, 1995, San Jose, California, United States
• 3: John M. Cohn, Analog Device-Level Layout Automation, Kluwer Academic Publishers, Norwell, MA, 2000
• 4: J. Cohn, et al. KOAN/ANAGRAMII: New Tools for Device-Level Analog Layout. IEEE J. Solid-State Circuits, 26(3):330--342, 1991.
• 5: K. Lampaert, G. Gielen, and W. Sansen. A Performance-driven Placement Tool for Analog Integrated Circuits. IEEE J. Solid-State Circuits, 30(7):773--780, 1995.
• 6: E. Malavasi, E. Charbon, E. Felt, and A. Sangiovanni-Vincentelli. Automation of IC Layout with Analog Constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(8):923--942, 1996.
• 7: F. Balasa and K. Lampaert. Symmetry within the Sequence-Pair Representation in the Constext of Placement for Analog Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 19(7):712--731, 2000.
• 8: Yingxin Pang , Florin Balasa , Koen Lampaert , Chung-Kuan Cheng, Block placement with symmetry constraints based on the O-tree non-slicing representation, Proceedings of the 37th conference on Design automation, p.464-467, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337545]
• 9: F. Balasa, S.-C. Maruvada, and K. Krishnamoorthy. On the Exploration of the Solution Space in Analog Placement with Symmetry Constraints. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 23(2):177--191, 2004.
• 10: Yiu-Cheong Tam , Evangeline F. Y. Young , Chris Chu, Analog placement with symmetry and other placement constraints, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233571]