A methodology for fast and accurate yield factor estimation during global routing

ABSTRACT

In this paper, a novel and computationally efficient methodology to accurately estimate key yield factors during the global routing stage is presented. Such an yield factor estimator at the global routing stage is essential since it can used to either get an early estimate of the final yield of the same design (i.e. the yield after applying the required sequence of detailed routing and post-routing yield optimizations) and/or to improve the final yield of the design by making the solution at the end of global routing more amenable to post-routing yield optimizations. The proposed yield factor estimator is inherently flexible and can easily be programmed to estimate during global routing a variety of key yield factors of the same design after a typical sequence of detailed routing and representative post-routing yield optimizations has been applied. Examples are provided to show how the yield factor estimator can be used to predict short and open critical area and metal density after typical yield optimization solutions like wire-spreading, wire-widening and metal filling, respectively. Experimental results presented in the paper show that the proposed yield factor estimator can predict final yield factor hotspots/values with a high degree of accuracy. The proposed estimator is also shown to be more suited for the purpose of yield factor estimation compared with typical metrics at the global routing stage like congestion.

REFERENCES

• 1: Dirk Müller, Optimizing yield in global routing, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233598]
• 2: W. Kuo and T. Kim. An overview of manufacturing yield and reliability modeling for semiconductor products. In Proceedings of IEEE, 87(8):1329--1344, 1999.
• 3: W. Maly , H. Heineken , J. Khare , P. K. Nag, Design for manufacturability in submicron domain, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.690-697, November 10-14, 1996, San Jose, California, United States
• 4: Y. Fei amd P. Simon and. Maly. New yield models for DSM manufacturing. In International Electron Devices Meeting (IEDM), 2000.
• 5: Subarna Sinha , Qing Su , Linni Wen , Frank Lee , Charles Chiang , Yi-Kan Cheng , Jin-Lien Lin , Yu-Chyi Harn, A New Flexible Algorithm for Random Yield Improvement, Proceedings of the 8th International Symposium on Quality Electronic Design, p.795-800, March 26-28, 2007 [doi>10.1109/ISQED.2007.18]
• 6: R. Tian, D. Wong and R. Boone, Model-based Dummy Feature Placement for Oxide Chemical-Mechanical Polishing Manufacturability. In IEEE Transactions on CAD, 2001.
• 7: A. B. Kahng , G. Robins , A. Singh , A. Zelikovsky, New and Exact Filling Algorithms for Layout Density Control, Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance', p.106, January 10-13, 1999
• 8: Yu Chen , Andrew B. Kahng , Gabriel Robins , Alex Zelikovsky, Monte-Carlo algorithms for layout density control, Proceedings of the 2000 conference on Asia South Pacific design automation, p.523-528, January 2000, Yokohama, Japan [doi>10.1145/368434.368778]
• 9: Yu Chen , Andrew B. Kahng , Gabriel Robins , Alexander Zelikovsky, Practical iterated fill synthesis for CMP uniformity, Proceedings of the 37th conference on Design automation, p.671-674, June 05-09, 2000, Los Angeles, California, United States [doi>10.1145/337292.337610]
• 10: Xin Wang , Charles C. Chiang , Jamil Kawa , Qing Su, A Min-Variance Iterative Method for Fast Smart Dummy Feature Density Assignment in Chemical-Mechanical Polishing, Proceedings of the 6th International Symposium on Quality of Electronic Design, p.258-263, March 21-23, 2005 [doi>10.1109/ISQED.2005.8]
• 11: Subarna Sinha , Jianfeng Luo , Charles Chiang, Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper Process, Proceedings of the 2007 conference on Asia South Pacific design automation, p.1-6, January 23-26, 2007 [doi>10.1109/ASPDAC.2007.357783]
• 12: M. R. Becer, D. Blaauw, R. Panda and I. N. Hajj, Early Probabilistic Noise Estimation for Capacitively Coupled Interconnects. In IEEE Transactions on CAD, March 2003.