Timing variation-aware high-level synthesis

ABSTRACT

The timing closure problem is one of the most important problems in the design automation. However, the rapid increase of the impact of the process variation on circuit timing makes the problem much more complicated and unpredictable to tackle in synthesis. This work addresses a new problem of high-level synthesis (HLS) that effectively takes into account the timing variation. Specifically, the work addresses the following four problem: (1) how can the statistical static timing analysis (SSTA) used in logic synthesis be modified and applied to the delay and yield computation in HLS? (2) how does the resource binding affect yield? (3) how does the scheduling affect yield? (4) how can scheduling and resource binding tasks be combined together to efficiently solve the problem with the objective of minimizing latency under yield constraint?

REFERENCES

• 1: Shekhar Borkar , Tanay Karnik , Siva Narendra , Jim Tschanz , Ali Keshavarzi , Vivek De, Parameter variations and impact on circuits and microarchitecture, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA [doi>10.1145/775832.775920]
• 2: Hongliang Chang , Sachin S. Sapatnekar, Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.621, November 09-13, 2003 [doi>10.1109/ICCAD.2003.129]
• 3: C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , S. Narayan, First-order incremental block-based statistical timing analysis, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996663]
• 4: A. Agarwal, V. Zolotov, and D. T. Blaauw, "Statistical timing analysis using bounds and selective enumeration," IEEE TCAD, pp. 1243--1260, September 2003.
• 5: Michael Orshansky , Arnab Bandyopadhyay, Fast statistical timing analysis handling arbitrary delay correlations, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996664]
• 6: Rajeev Rao , Ashish Srivastava , David Blaauw , Dennis Sylvester, Statistical analysis of subthreshold leakage current for VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.2, p.131-139, February 2004 [doi>10.1109/TVLSI.2003.821549]
• 7: Siva Narendra , Vivek De , Shekhar Borkar , Dimitri Antoniadis , Anantha Chandrakasan, Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA [doi>10.1145/566408.566415]
• 8: Sreeja Raj , Sarma B. K. Vrudhula , Janet Wang, A methodology to improve timing yield in the presence of process variations, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996694]
• 9: Seung Hoon Choi , Bipul C. Paul , Kaushik Roy, Novel sizing algorithm for yield improvement under process variation in nanometer technology, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996695]
• 10: Ashish Srivastava , Dennis Sylvester , David Blaauw, Statistical optimization of leakage power considering process variations using dual-Vth and sizing, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA [doi>10.1145/996566.996775]
• 11: A. Davoodi , V. Khandelwal , A. Srivastava, Variability inspired implementation selection problem, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.423-427, November 07-11, 2004 [doi>10.1109/ICCAD.2004.1382612]
• 12: W.-L. Hung , Xiaoxia Wu , Yuan Xie, Guaranteeing performance yield in high-level synthesis, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California [doi>10.1145/1233501.1233561]
• 13: A. Srivastava, D. Sylvester, and D. Blaauw, Statistical analysis and optimization for VLSI: timing and power, Springer 2005.
• 14: Jing-Jia Liou , Kwang-Ting Cheng , Sandip Kundu , Angela Krstic, Fast statistical timing analysis by probabilistic event propagation, Proceedings of the 38th conference on Design automation, p.661-666, June 2001, Las Vegas, Nevada, United States [doi>10.1145/378239.379043]
• 15: Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill Higher Education, 1994
• 16: Kunhyuk Kang , Bipul C. Paul , Kaushik Roy, Statistical Timing Analysis using Levelized Covariance Propagation, Proceedings of the conference on Design, Automation and Test in Europe, p.764-769, March 07-11, 2005 [doi>10.1109/DATE.2005.279]