Reducing cache energy consumption by tag encoding in embedded processors

ABSTRACT

This paper presents a new technique eliminating redundant cache tag and data accesses to reduce energy consumption. We assign a register to each tag in a cache to represent its state. Before starting an access, we can check the tag states in the target cache set to determine which way(s) should be accessed and which should not. Through this method, almost all the accesses in the I-cache can be directed to the target cache way immediately for most benchmark programs. For a 2-way set-associative cache, the energy consumption can be reduced by 76.6% compared with conventional cache architecture, and by 39.8% compared with Block Buffering, a simple but well-known technique. Besides, this approach does not require any special circuitry internal to the cache RAM such as row or column activation mechanisms. This is considered an important advantage in industry because of its easy implementation.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.3 MEMORY STRUCTURES
      B.3.2 Design Styles
          Subjects: Cache memories

General Terms:
Design, Experimentation, Performance

Keywords:
cache, embedded processors, low power design, tag encoding