Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	P. Agrawal and V. D. Agrawal, Probabilistic Analysis of Random Test Generation Method for lrredundant Combinational Logic Networks, IEEE Trans. on Computers, Vol. C-24, July 1975, pp. 691-695.
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	3	F. Brglez and H. Fujiwara, A neutral netlist o.f ten combinational benchmark circuits and a target simulator in Fortran, Proc. IEEE Intl. Sym. on Circuits and Systems, June 1985, Kyoto, Japan.
	4	Kenneth M. Butler , M. Ray Mercer, The influences of fault type and topology on fault model performance and the implications to test and testable design, Proceedings of the 27th ACM/IEEE conference on Design automation, p.673-678, June 24-27, 1990, Orlando, Florida, United States  [doi>10.1145/123186.123436]
	5	W. Feller,An Introduction to Probability Theory and its Applicaions, Vol-I, John Wiley & Sons, New York, NY. 1968.
	6	N. L. Johnson and S. Kotz, Discrete Distributions, Houghton Mifflin Co., Boston, MA. 1969.
	7	L. Lipsky , S. C. Seth, Signal Probabilities in AND-OR Trees, IEEE Transactions on Computers, v.38 n.11, p.1558-1563, November 1989  [doi>10.1109/12.42125]
	8	E. J. McCluskey, Built-In Self-Test Techniques, Design and Test of Computers, Vol. 2, No. 2, pp. 21-28, 1985.
	9	E. J. McCluskey, S. Makar, S. Mourad and K. D. Wagner, Probability Models .for Pseudorandom Test Sequences, IEEE Trans. on Computer Aided Design, Vol. 7, Jan. 1988, pp 68-74.
	10	J. Savir, G. S. Ditlow and P. H. Bardell, Random Pattern Testability, IEEE Trans. on Computers, Vol. C-33, Jan. 1984, pp. 79-90.
	11	S. C. Seth, L. Pan and V. D. Agrawal, PREDICT: Probabilistic Estimation of Digital Circuit Testability, Proc. FTCS-15, 1985, pp. 220-225.

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