Dynamic prediction of critical paths and nets for constructive timing-driven placement

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Dynamic prediction of critical paths and nets for constructive timing-driven placement

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Annual ACM IEEE Design Automation Conference archive
Proceedings of the 28th ACM/IEEE Design Automation Conference table of contents

San Francisco, California, United States

Pages: 632 - 635

Year of Publication: 1991

ISBN:0-89791-395-7

Authors

Suphachai Sutanthavibul	IBM Corp, Data System Division, Neighborhood Road, Kingston, NY and Computer Science Department, University of Minnesota, Minneapolis, Minnesota
Eugene Shragowitz	Computer Science Department, University of Minnesota, Minneapolis, Minnesota

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 5

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references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	ASA85	T. Asano , S. Sato, Long path enumeration algorithms for timing verification on large digital systems, Graph theory with applications to algorithms and computer science, John Wiley & Sons, Inc., New York, NY, 1985
	BUR85	Michael Burstein , Mary N. Youssef, Timing influenced layout design, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.124-130, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317845]
	DON90	Wilm E. Donath , Reini J. Norman , Bhuwan K. Agrawal , Stephen E. Bello , Sang Yong Han , Jerome M. Kurtzberg , Paul Lowy , Roger I. McMillan, Timing driven placement using complete path delays, Proceedings of the 27th ACM/IEEE conference on Design automation, p.84-89, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123232]
	DUN87	A. E. Dunlop , V. D. Agrawal , D. N. Deutsch , M. F. Jukl , P. Kozak , M. Wiesel, Chip layout optimization using critical path weighting, Proceedings of the 21st conference on Design automation, p.133-136, June 25-27, 1984, Albuquerque, New Mexico, United States
	HIT82	R.B. Hitchcock, Sr., Gordon L. Smith, and David D. Cheng, "'l'iming Analysis of Computer Hardware", IBM J. RES. DEVELOP., VOL. 26, NO. 1, pp. 100-116, 1982
	HOR84	Ellis Horowitz , Sartaj Sahni, Fundamentals of Computer Alori, W. H. Freeman & Co., New York, NY, 1978
	JAC89	M. A. B. Jackson , E. S. Kuh, Performance-driven placement of cell based IC's, Proceedings of the 26th ACM/IEEE conference on Design automation, p.370-375, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74444]
	KIR66	I'.1. Kirkpatrick and N. R. Clark, "PERT as an Aid to Logic Design", IBM J. Res. Develop., Vol. 10, No. 2, pp. 135-141, 1966
	MAR89	M. Marek-Sadowska, S.P. Lin, "Timing Driven Placement', Prec. international Conference on Computer Aided Design, pp. 94-97, 1989.
	NAI89	R. Nair, and et al., "Generation of Performance constraints fbr layout~, IEEE Transaction on CAD, Vol. CAD-8, No. 8, pp. 860-874, August 1989.
	OGA86	Yasushi Ogawa , Tatsuki Ishii , Yoichi Shiraishi , Hidekazu Terai , Tokinori Kozawa , Kyoji Yuyama , Kyoji Chiba, Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.404-410, July 1986, Las Vegas, Nevada, United States
	PRA89	S. Prasitjutrakul , W. J. Kubitz, Path-delay constrained floorplanning: a mathematical programming approach for initial placement, Proceedings of the 26th ACM/IEEE conference on Design automation, p.364-369, June 25-28, 1989, Las Vegas, Nevada, United States [doi>10.1145/74382.74443]
	SUT90	Suphachai Sutanthavibul , Eugene Shragowitz, An adaptive timing-driven layout for high speed VLSI, Proceedings of the 27th ACM/IEEE conference on Design automation, p.90-95, June 24-27, 1990, Orlando, Florida, United States [doi>10.1145/123186.123233]
	YOU90	Habib Youssef, Timing issues in cell-based VLSI design, University of Minnesota, Minneapolis, MN, 1990

CITED BY 5

	Michael Hutton , Khosrow Adibsamii , Andrew Leaver, Adaptive delay estimation for partitioning-driven PLD placement, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.11 n.1, p.60-63, February 2003
	R.-B. Lin , E. Shragowitz, Fuzzy logic approach to placement problem, Proceedings of the 29th ACM/IEEE conference on Design automation, p.153-158, June 08-12, 1992, Anaheim, California, United States
	Michael Hutton , Khosrow Adibsamii , Andrew Leaver, Timing-driven placement for hierarchical programmable logic devices, Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, p.3-11, February 2001, Monterey, California, United States
	William Swartz , Carl Sechen, Timing driven placement for large standard cell circuits, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.211-215, June 12-16, 1995, San Francisco, California, United States
	Min Xu , Fadi J. Kurdahi, Layout-driven RTL binding techniques for high-level synthesis using accurate estimators, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.4, p.312-343, Oct. 1997