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ABSTRACT
In this paper, a new method for evolving simple electronic circuits is discussed, with the aim of improving the reliability and performance of basic circuit blocks. Next-generation CMOS device models will be used in the simulation of circuits. Circuits are mapped to a grid layout which reflects the appearance of conventional schematic blocks. The performance of the system at designing passive low-pass filters is discussed, with an outline given of the intended future steps, towards the goal of integrating sub 100 nm MOSFET models into the circuits.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[doi> 10.1145/331697.331742]
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