ACM Home Page
Please provide us with feedback. Feedback
Interactive presentation: A process splitting transformation for Kahn process networks
Full text PdfPdf (248 KB)
Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Nice, France
SESSION: Compiler techniques for customisable architectures table of contents
Pages: 1355 - 1360  
Year of Publication: 2007
ISBN:978-3-9810801-2-4
Authors
Sjoerd Meijer  Leiden Institute of Advanced Computer Science (LiACS), CA Leiden, The Netherlands
Bart Kienhuis  Leiden Institute of Advanced Computer Science (LiACS), CA Leiden, The Netherlands
Alex Turjan  NXP Semiconductors, AE Eindhoven, The Netherlands
Erwin de Kock  NXP Semiconductors, AE Eindhoven, The Netherlands
Sponsors
: IEEE Council on Electronic Design Automation (CEDA)
: The EDA Consortium
EDAA : European Design and Automation Association
SIGDA : ACM Design Automation
RAS : RAS
: The IEEE Computer Society TTTC
: ECSI
Publisher
EDA Consortium  San Jose, CA, USA
Bibliometrics
Downloads (6 Weeks): 5,   Downloads (12 Months): 37,   Citation Count: 1
Additional Information:

abstract   references   cited by   collaborative colleagues  

Tools and Actions: Review this Article  

ABSTRACT

In this paper we present a process splitting transformation for Kahn process networks. Running applications written in this parallel program specification on a multiprocessor architecture does not guarantee that the runtime requirements are met. Therefore, it may be necessary to further analyze and optimize Kahn process networks. In this paper, we will present a four-step transformation that results in a functionally equivalent process network, but with a changed and optimized network structure. The class of networks that can be handled is not restricted to static networks. The novelty of this approach is that it can also handle processes with dynamic program statements. We will illustrate the transformation prototyped in GCC for a JPEG decoder, showing a 21% performance improvements.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
2
3
 
4
P. Feautrier. Parametric integer programming. RAIRO Recherche Opérationnelle, 22(3):243--268, 1988.
 
5
G. Kahn. The semantics of a simple language for parallel programming. In J. L. Rosenfeld, editor, Information processing, pages 471--475, Stockholm, Sweden, Aug 1974. North Holland, Amsterdam.
6
 
7
D. Pham et al. The design and implementation of a first-generation cell processor. In In ISSCC Digest of Technical Papers, pages p. 184--5, 2005.
 
8
 
9
Edwin Rijpkema. Modeling Task Level Parallelism in Piece-wise Regular Programs, 2002. PhD thesis, Leiden University, The Netherlands.
10
 
11
Paul Stravers and Jan Hoogerbrugge. Homogeneous multiprocessing and the future of silicon design paradigms. In In Prce. International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA 2001), April 2001.
12
 
13
 
14
Claudiu Zissulescu, Bart Kienhuis, and Ed F. Deprettere. Increasing pipelined ip core utilization in process networks using exploration. In FPL, pages 690--699, 2004.

Collaborative Colleagues:
Sjoerd Meijer: colleagues
Bart Kienhuis: colleagues
Alex Turjan: colleagues
Erwin de Kock: colleagues