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Polynomial-time subgraph enumeration for automated instruction set extension
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Nice, France
SESSION: Compiler techniques for customisable architectures table of contents
Pages: 1331 - 1336  
Year of Publication: 2007
ISBN:978-3-9810801-2-4
Authors
Paolo Bonzini  University of Lugano (USI), Switzerland
Laura Pozzi  University of Lugano (USI), Switzerland
Sponsors
: IEEE Council on Electronic Design Automation (CEDA)
: The EDA Consortium
EDAA : European Design and Automation Association
SIGDA : ACM Design Automation
RAS : RAS
: The IEEE Computer Society TTTC
: ECSI
Publisher
EDA Consortium  San Jose, CA, USA
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Downloads (6 Weeks): 4,   Downloads (12 Months): 31,   Citation Count: 3
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ABSTRACT

This paper proposes a novel algorithm that, given a data-flow graph and an input/output constraint, enumerates all convex subgraphs under the given constraint in polynomial time with respect to the size of the graph. These subgraphs have been shown to represent efficient Instruction Set Extensions for customizable processors. The search space for this problem is inherently polynomial but, to our knowledge, this is the first paper to prove this and to present a practical algorithm for this problem with polynomial complexity. Our algorithm is based on properties of convex subgraphs that link them to the concept of multiple-vertex dominators. We discuss several pruning techniques that, without sacrificing the optimality of the algorithm, make it practical for data-flow graphs of a thousands nodes or more.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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E. Dubrova, M. Teslenko, and A. Martinelli. On relation between non-disjoint decomposition and multiple-vertex dominators. In Proc. of ISCAS, 2004.
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L. Pozzi, K. Atasu, and P. Ienne. Optimal and approximate algorithms for the extension of embedded processor instruction sets. In IEEE TCAD, July 2006.
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P. Bonzini and L. Pozzi Polynomial-time subgraph enumeration for automated instruction set extension. TR 2006/07, University of Lugano, 2006. http://www.inf.unisi.ch/file/pub/15/bonzini-pozzi-2006-07.pdf

Collaborative Colleagues:
Paolo Bonzini: colleagues
Laura Pozzi: colleagues