| Polynomial-time subgraph enumeration for automated instruction set extension |
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Design, Automation, and Test in Europe
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Proceedings of the conference on Design, automation and test in Europe
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Nice, France
SESSION: Compiler techniques for customisable architectures
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Pages: 1331 - 1336
Year of Publication: 2007
ISBN:978-3-9810801-2-4
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EDA Consortium
San Jose, CA, USA
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Downloads (6 Weeks): 4, Downloads (12 Months): 31, Citation Count: 3
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ABSTRACT
This paper proposes a novel algorithm that, given a data-flow graph and an input/output constraint, enumerates all convex subgraphs under the given constraint in polynomial time with respect to the size of the graph. These subgraphs have been shown to represent efficient Instruction Set Extensions for customizable processors. The search space for this problem is inherently polynomial but, to our knowledge, this is the first paper to prove this and to present a practical algorithm for this problem with polynomial complexity. Our algorithm is based on properties of convex subgraphs that link them to the concept of multiple-vertex dominators. We discuss several pruning techniques that, without sacrificing the optimality of the algorithm, make it practical for data-flow graphs of a thousands nodes or more.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Partha Biswas , Sudarshan Banerjee , Nikil Dutt , Laura Pozzi , Paolo Ienne, ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement, Proceedings of the conference on Design, Automation and Test in Europe, p.1246-1251, March 07-11, 2005
[doi> 10.1109/DATE.2005.191]
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Hoon Choi , Jong-Sun Kim , Chi-Won Yoon , In-Cheol Park , Seung Ho Hwang , Chong-Min Kyung, Synthesis of Application Specific Instructions for Embedded DSP Software, IEEE Transactions on Computers, v.48 n.6, p.603-614, June 1999
[doi> 10.1109/12.773797]
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Nathan Clark , Amir Hormati , Scott Mahlke , Sami Yehia, Scalable subgraph mapping for acyclic computation accelerators, Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems, October 22-25, 2006, Seoul, Korea
[doi> 10.1145/1176760.1176779]
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E. Dubrova, M. Teslenko, and A. Martinelli. On relation between non-disjoint decomposition and multiple-vertex dominators. In Proc. of ISCAS, 2004.
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L. Pozzi, K. Atasu, and P. Ienne. Optimal and approximate algorithms for the extension of embedded processor instruction sets. In IEEE TCAD, July 2006.
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P. Bonzini and L. Pozzi Polynomial-time subgraph enumeration for automated instruction set extension. TR 2006/07, University of Lugano, 2006. http://www.inf.unisi.ch/file/pub/15/bonzini-pozzi-2006-07.pdf
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CITED BY 3
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Ya-shuai Lü , Li Shen , Li-bo Huang , Zhi-ying Wang , Nong Xiao, Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
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