Circuit-level modeling and detection of metallic carbon nanotube defects in carbon nanotube FETs

ABSTRACT

Carbon Nanotube Field Effect Transistors (CNTFET) are promising nano-scaled devices for implementing high performance, very dense and low power circuits. The core of a CNTFET is a carbon nanotube. Its conductance property is determined by the so-called chirality of the tube; chirality is difficult to control during manufacturing. This results in conducting (metallic) nanotubes and defective CNTFETs similar to stuck-on (SON or source-drain short) faults, as encountered in classical MOS devices. This paper studies this phenomenon by using layout information and presents modeling and detection methodologies for nano-scaled defects arising from the presence of metallic carbon nanotubes. For CNTFET-based circuits (e.g. intramolecular), these defects are analyzed using a traditional stuck-at fault model. This analysis is applicable to primitive and complex gates. Simulation results are presented for detecting modeled metallic nanotube faults in CNTFETs using a single stuck-at fault test set. A high coverage is achieved (~98%).

REFERENCES

• 1: S. Ijima "Helical Microtubules of Graphitic Carbon," Nature, Vol. 354, pp. 56--58, Nov. 1991.
• 2: V. Derycke, R. Martle, J. Appenzeller, and P. Avouris, "Carbon Nanotubes Inter- and Interamolecular Logic Gates," Nano Letters, Vol. 1, pp. 453--456, 2001.
• 3: P. Avouris, J. Appenzeller, R. Martel, and S. J. Wind, "Carbon Nanotube Electronics," Proc. of IEEE, Vol. 91, No. 11, pp. 1772--1784, Nov. 2003.
• 4: P. L. McEuen, M. S. Fuhrer, and H. Park "Single-Walled Carbon Nanotube Electronics," IEEE Tran. on Nanotechnology, Vol. 1, No. 1, pp. 78--85, March 2002.
• 5: S. J. Tans, A. R. M. Verschueren, and C. Dekker, "Room-Temperature Transistor based on a Single Carbon Nanotube," Nature, Vol. 393, pp. 49--52, May 1998.
• 6: A. Bachtold, P. Hadley, T. Nakanishi, and C. Dekker, "Logic Circuits with Carbon Nanotube Transistors," Science, Vol. 294, No. 5545, pp. 1317--1320, Oct. 2001.
• 7: S. J. Wind, J. Appenzeller, R. Martel, V. Derycke, and Ph. Avouris, "Vertical Scaling of Carbon Nanotube Field-Effect Transistors using Top Gate Electrodes," Applied Phys. Lett., Vol. 80, No. 20, pp. 3817--3819, May 2002.
• 8: C. L. Cheung, A. Kurtz, H. Park, C. M. Lieber, "Diameter-Controlled Synthesis of Carbon Nanotubes," J. Phys. Chem. B, Vol. 106, pp. 2429--2433, 2002.
• 9: P. G. Collins, M. S. Arnold, and P. Avouris "Engineering Carbon Nanotubes Using Electrical Breakdown," Science, Vol. 292, pp. 706--709, 2001.
• 10: T. Uehara and W. M. vanCleemput, "Optimal Layout of CMOS Functional Arrays," IEEE Tran. on Computer., Vol. C-30, No. 5, pp. 305--312, May 1981.
• 11: R. L. Maiasz , J. P. Hayes, Layout optimization of CMOS functional cells, Proceedings of the 24th ACM/IEEE conference on Design automation, p.544-551, June 28-July 01, 1987, Miami Beach, Florida, United States [doi>10.1145/37888.37969]
• 12: B. S. Carlson, C. Y. R. Chen, and U. Singh, "Optimal Cell Generation for Dual Independent Layout Styles," IEEE Tran. on Computer Aided Design, Vol. 10, No. 6, pp. 770--782, June 1991.
• 13: S. Hwang, R. Rajsuman, and S. Davidson, "IDDQ Detection of CMOS Bridging Faults by Stuck-At Fault Tests," Proc. of IEEE Intl. Conf. on VLSI Design, pp. 183--186, 1994.
• 14: Ilker Hamzaoglu , Janak H. Patel, Test set compaction algorithms for combinational circuits, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.283-289, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288615]

INDEX TERMS

Keywords:
CNT, CNTFET, carbon nanotube, defect modeling, fault detection, nanotechnology