Interactive presentation: Evaluation of test measures for LNA production testing using a multinormal statistical model

ABSTRACT

For Design-For-Test (DFT) purposes, analogue and mixed-signal testing has to cope with the difficulty of test evaluation before production. This paper aims at evaluating test measures for RF components in order to optimize production test sets and thus reduce test cost. For this, we have first developed a statistical model of the performances and possible test measures of the Circuit Under Test (a Low Noise Amplifier). The statistical multi-normal model is derived from data obtained using Monte-Carlo circuit simulation (five hundred iterations). This statistical model is then used to generate a larger circuit population (one million instances) from which test metrics can be estimated with ppm precision at the design stage, considering just process deviations. With the use of this model, a trade-off between defect level and yield loss resulting from process deviations is used to set test limits. After fixing test limits, we have carried out a fault simulation campaign to verify the suitability of the different test measurements, targeting both catastrophic and single parametric faults. Catastrophic faults are modelled by shorts and opens. A parametric fault is defined as the minimum value of a physical parameter that causes a specification to be violated. Test metrics are then evaluated for the LNA case-study. As a result, test metrics for functional measurements such as S-parameters and Noise Figure are compared with low cost test measurements such as RMS and peak-to-peak current consumption and output voltage, input/output impedance, and the correlation between current consumption and output voltage.

REFERENCES

• 1: Stephen Sunter , Naveena Nagi, Test Metrics for Analog Parametric Faults, Proceedings of the 1999 17TH IEEE VLSI Test Symposium, p.226, April 26-30, 1999
• 2: A. Bounceur, S. Mir, L. Rolíndez, and E. Simeu, "A CAT platform for analogue and mixed-signal test evaluation and optimization", Digest of Papers of the European Test Symposium, Southampton, UK, 2006, pp. 217--222.
• 3: J. Pineda de Gyvez, G. Gronthoud, and R. Amine, "VDD ramp testing for RF circuits", IEEE International Test Conference, Charlotte, USA, October 2003, pp. 651--658.
• 4: J-Y. Ryu, B. C. Kim, S-T. Kim, and V. Varadarajan, "Novel defect testing of RF front end using input matching measurement", In 9th International Mixed-Signal Testing Workshop, Seville, Spain, June 2003, pp. 31--34.
• 5: Antonija Soldo , Anand Gopalan , P. R. Mukund , Martin Margala, A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems, Proceedings of the 17th International Conference on VLSI Design, p.1023, January 05-09, 2004
• 6: J. Machado, "Low-Power In Circuit Testing of a LNA", In 11th International Mixed-Signal Testing Workshop, Cannes, France, June 2005, pp. 206--210.
• 7: R. Voorakaranam , S. Cherubal , A. Chatterjee, A Signature Test Framework for Rapid Production Testing of RF Circuits, Proceedings of the conference on Design, automation and test in Europe, p.186, March 04-08, 2002
• 8: N. Nagi, and J. Abraham, "Hierachical Fault Modeling for analog and mixed-signal circuits", In IEEE 10th VLSI Test Symposium, Atlantic City, USA, April 1992, pp. 96--101.
• 9: R. Kheriji , V. Danelon , J. L. Carbonero , S. Mir, Optimising Test Sets for a Low Noise Amplifier with a Defect-Oriented Approach, Proceedings of the conference on Design, Automation and Test in Europe, p.170-171, March 07-11, 2005 [doi>10.1109/DATE.2005.233]
• 10: J. T. de Sousa, F. M. Gonçalves, J. P. Teixeira, C. Marzocca, F. Corsi, and T. W. Williams, "Defect level evaluation in an IC design environment", In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 10, October 1996, pp. 1286--1293.