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On test generation by input cube avoidance
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Source Design, Automation, and Test in Europe archive
Proceedings of the conference on Design, automation and test in Europe table of contents
Nice, France
SESSION: Test generation for diagnosis, scan testing and advanced memory fault models table of contents
Pages: 522 - 527  
Year of Publication: 2007
ISBN:978-3-9810801-2-4
Authors
Irith Pomeranz  Purdue University, W. Lafayette, IN
Sudhakar M. Reddy  University of Iowa, Iowa City, IA
Sponsors
: IEEE Council on Electronic Design Automation (CEDA)
: The EDA Consortium
EDAA : European Design and Automation Association
SIGDA : ACM Design Automation
RAS : RAS
: The IEEE Computer Society TTTC
: ECSI
Publisher
EDA Consortium  San Jose, CA, USA
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Downloads (6 Weeks): 2,   Downloads (12 Months): 9,   Citation Count: 1
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ABSTRACT

Test generation procedures attempt to assign values to the inputs of a circuit so as to detect target faults. We study a complementary view whereby the goal is to identify values that should not be assigned to inputs in order not to prevent faults from being detected. We describe a procedure for computing input cubes (or incompletely specified input vectors) that should be avoided during test generation for target faults. We demonstrate that avoiding such input cubes leads to the detection of target faults after the application of limited numbers of random input vectors. This indicates that explicit test generation is not necessary once certain input values are precluded. Potential uses of the computed input cubes are in a test generation procedure to reduce the search space, and during built-in test generation to preclude input vectors that will not lead to the detection of target faults.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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P. Goel and B. C. Rosales, "Test Generation and Dynamic Compaction of Tests", in Proc. Test Conf., 1979 pp. 189--192.
 
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J.-S. Chang and C.-S. Lin, "Test Set Compaction for Combinational Circuits", in Proc. Asian Test Symp., 1992, pp. 20--25.
 
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Y. Matsunaga, "MINT -An Exact Algorithm for Finding Minimum Test Sets", IEICE Trans. Fundamentals., vol. E76-A, No. 10, Oct. 1993, pp. 1652--1658.
 
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S. Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, "Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits", IEEE Trans. on Computer-Aided Design, Dec. 1995, pp. 1496--1504.
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V. D. Agrawal, K. T. Cheng, and P. Agrawal, "A Directed Search Method for Test Generation Using Concurrent Simulator," IEEE Trans, on Computer-Aided Design, Feb. 1989, pp. 131--138.
 
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Collaborative Colleagues:
Irith Pomeranz: colleagues
Sudhakar M. Reddy: colleagues