An effective on-chip preloading scheme to reduce data access penalty

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An effective on-chip preloading scheme to reduce data access penalty

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Conference on High Performance Networking and Computing archive
Proceedings of the 1991 ACM/IEEE conference on Supercomputing table of contents

Albuquerque, New Mexico, United States

Pages: 176 - 186

Year of Publication: 1991

ISBN:0-89791-459-7

Authors

Jean-Loup Baer	Department of Computer Science and Engineering, University of Washington, Seattle, WA
Tien-Fu Chen	Department of Computer Science and Engineering, University of Washington, Seattle, WA

Sponsors

IEEE : Institute of Electrical and Electronics Engineers
SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 6, Downloads (12 Months): 121, Citation Count: 93

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Anita Borg , R. E. Kessler , David W. Wall, Generation and analysis of very long address traces, Proceedings of the 17th annual international symposium on Computer Architecture, p.270-279, May 28-31, 1990, Seattle, Washington, United States
	2	Edward H. Gornish , Elana D. Granston , Alexander V. Veidenbaum, Compiler-directed data prefetching in multiprocessors with memory hierarchies, Proceedings of the 4th international conference on Supercomputing, p.354-368, June 11-15, 1990, Amsterdam, The Netherlands
	3	David A. Patterson , John L. Hennessy, Computer architecture: a quantitative approach, Morgan Kaufmann Publishers Inc., San Francisco, CA, 1990
	4	Mark Donald Hill , Alan Jay Smith, Aspects of cache memory and instruction buffer performance, 1987
	5	Norman P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, Proceedings of the 17th annual international symposium on Computer Architecture, p.364-373, May 28-31, 1990, Seattle, Washington, United States
	6	David Kroft, Lockup-free instruction fetch/prefetch cache organization, Proceedings of the 8th annual symposium on Computer Architecture, p.81-87, May 12-14, 1981, Minneapolis, Minnesota, United States
	7	J. K. F. Lee and A. J. Smith. Branch prediction strategies and branch target buffer design. Computer, pages 6-22, January 1984.
	8	R. L. Lee, P-C. Yew, and D. H. Lawrie. Data prefetching in shared memory multiprocessors. In Proc. of the Int. Conf. on Parallel Processing, pages 28-31, 1987.
	9	Chris H. Perteberg , Alan J Smith, Branch Target Buffer Design and Optimization, University of California at Berkeley, Berkeley, CA, 1989
	10	A. K. Porterfield. Software molt,~)ds for improvement of cache performance on supercomputer application. Technical Report COMP TR 89-93, Rice University, May 1989.
	11	Steven Przybylski, The performance impact of block sizes and fetch strategies, Proceedings of the 17th annual international symposium on Computer Architecture, p.160-169, May 28-31, 1990, Seattle, Washington, United States
	12	Alan Jay Smith, Cache Memories, ACM Computing Surveys (CSUR), v.14 n.3, p.473-530, Sept. 1982 [doi>10.1145/356887.356892]
	13	James E. Smith, Decoupled access/execute computer architectures, Proceedings of the 9th annual symposium on Computer Architecture, p.112-119, April 26-29, 1982, Austin, Texas, United States
	14	The Perfect Club, et al. The Perfect Club benchmarks: Effective performance evaluation of supercomputers. Int. J. of Supercompuler Applications, 23(3):5-40, Fall 1989.

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	K. Nakazawa , H. Nakamura , H. Imori , S. Kawabe, Pseudo vector processor based on register-windowed superscalar pipeline, Proceedings of the 1992 ACM/IEEE conference on Supercomputing, p.642-651, November 16-20, 1992, Minneapolis, Minnesota, United States
	Edward S. Tam , Jude A. Rivers , Vijayalakshmi Srinivasan , Gary S. Tyson , Edward S. Davidson, Active Management of Data Caches by Exploiting Reuse Information, IEEE Transactions on Computers, v.48 n.11, p.1244-1259, November 1999
	Pablo Ibáñez , Víctor Viñals , José L. Briz , María J. Garzarán, Characterization and improvement of load/store cache-based prefetching, Proceedings of the 12th international conference on Supercomputing, p.369-376, July 1998, Melbourne, Australia
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	Y. Jégou , O. Temam, Speculative prefetching, Proceedings of the 7th international conference on Supercomputing, p.57-66, July 19-23, 1993, Tokyo, Japan
	Shlomit S. Pinter , Adi Yoaz, Tango: a hardware-based data prefetching technique for superscalar processors, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.214-225, December 02-04, 1996, Paris, France
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	S. Palacharla , R. E. Kessler, Evaluating stream buffers as a secondary cache replacement, ACM SIGARCH Computer Architecture News, v.22 n.2, p.24-33, April 1994
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	Marco Galluzzi , Ramón Beivide , Valentin Puente , José-Ángel Gregorio , Adrian Cristal , Mateo Valero, Evaluating kilo-instruction multiprocessors, Proceedings of the 3rd workshop on Memory performance issues: in conjunction with the 31st international symposium on computer architecture, p.72-79, June 20-20, 2004, Munich, Germany
	Hariprakash. G , Achutharaman. R , Amos R. Omondi, DSTRIDE: data-cache miss-address-based stride prefetching scheme for multimedia processors, Australian Computer Science Communications, v.23 n.4, p.62-70, January 2001
	Jin-Ho Lee , Min-Young Lee , Seong-Uk Choi , Myong-Soon Park, Reducing cache conflicts in data cache prefetching, ACM SIGARCH Computer Architecture News, v.22 n.4, p.71-77, Sept. 1994
	Luis M. Ramos , José Luis Briz , Pablo E. Ibáñez , Victor Viñals, Data prefetching in a cache hierarchy with high bandwidth and capacity, Proceedings of the 2006 workshop on MEmory performance: DEaling with Applications, systems and architectures, p.37-44, September 16-20, 2006, Seattle, Washington
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	Luis M. Ramos , José Luis Briz , Pablo E. Ibáñez , Victor Viñals, Data prefetching in a cache hierarchy with high bandwidth and capacity, ACM SIGARCH Computer Architecture News, v.35 n.4, September 2007
	R. Manikantan , R. Govindarajan, Focused prefetching: performance oriented prefetching based on commit stalls, Proceedings of the 22nd annual international conference on Supercomputing, June 07-12, 2008, Island of Kos, Greece
	Chang Joo Lee , Onur Mutlu , Veynu Narasiman , Yale N. Patt, Prefetch-Aware DRAM Controllers, Proceedings of the 2008 41st IEEE/ACM International Symposium on Microarchitecture, p.200-209, November 08-12, 2008
	Marius Pirvu , Laxmi Bhuyan, Hardware spatial forwarding for widely shared data, Proceedings of the 14th international conference on Supercomputing, p.264-273, May 08-11, 2000, Santa Fe, New Mexico, United States
	Todd C. Mowry , Monica S. Lam , Anoop Gupta, Design and evaluation of a compiler algorithm for prefetching, ACM SIGPLAN Notices, v.27 n.9, p.62-73, Sept. 1992
	Chengqiang Zhang , Sally A. McKee, Hardware-only stream prefetching and dynamic access ordering, Proceedings of the 14th international conference on Supercomputing, p.167-175, May 08-11, 2000, Santa Fe, New Mexico, United States
	Wei-Fen Lin , Steven K. Reinhardt , Doug Burger, Designing a Modern Memory Hierarchy with Hardware Prefetching, IEEE Transactions on Computers, v.50 n.11, p.1202-1218, November 2001
	Michael Bekerman , Stephan Jourdan , Ronny Ronen , Gilad Kirshenboim , Lihu Rappoport , Adi Yoaz , Uri Weiser, Correlated load-address predictors, ACM SIGARCH Computer Architecture News, v.27 n.2, p.54-63, May 1999
	Sanjeev Kumar , Christopher Wilkerson, Exploiting spatial locality in data caches using spatial footprints, ACM SIGARCH Computer Architecture News, v.26 n.3, p.357-368, June 1998
	Chi-Keung Luk , Todd C. Mowry, Compiler-based prefetching for recursive data structures, ACM SIGOPS Operating Systems Review, v.30 n.5, p.222-233, Dec. 1996
	Chia-Lin Yang , Alvin R. Lebeck, Push vs. pull: data movement for linked data structures, Proceedings of the 14th international conference on Supercomputing, p.176-186, May 08-11, 2000, Santa Fe, New Mexico, United States
	Koray Öner , Michel Dubois, Effects of memory latencies on non-blocking processor/cache architectures, Proceedings of the 7th international conference on Supercomputing, p.338-347, July 19-23, 1993, Tokyo, Japan
	Fredrik Dahlgren , Michel Dubois , Per Stenström, Sequential Hardware Prefetching in Shared-Memory Multiprocessors, IEEE Transactions on Parallel and Distributed Systems, v.6 n.7, p.733-746, July 1995
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	A. Mahjur , A. H. Jahangir , A. H. Gholamipour, On the performance of trace locality of reference, Performance Evaluation, v.60 n.1-4, p.51-72, May 2005
	Alex Pajuelo , Antonio González , Mateo Valero, Speculative execution for hiding memory latency, ACM SIGARCH Computer Architecture News, v.33 n.3, June 2005
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	Michael K. Gschwind , Thomas J. Pietsch, Vector prefetching, ACM SIGARCH Computer Architecture News, v.23 n.5, p.1-7, Dec. 1995
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	Jude A. Rivers , Edward S. Tam , Gary S. Tyson , Edward S. Davidson , Matt Farrens, Utilizing reuse information in data cache management, Proceedings of the 12th international conference on Supercomputing, p.449-456, July 1998, Melbourne, Australia
	Antonio González , Carlos Aliagas , Mateo Valero, A data cache with multiple caching strategies tuned to different types of locality, Proceedings of the 9th international conference on Supercomputing, p.338-347, July 03-07, 1995, Barcelona, Spain
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	Kourosh Gharachorloo , Anoop Gupta , John Hennessy, Hiding memory latency using dynamic scheduling in shared-memory multiprocessors, ACM SIGARCH Computer Architecture News, v.20 n.2, p.22-33, May 1992
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	Nathalie Drach, Hardware implementation issues of data prefetching, Proceedings of the 9th international conference on Supercomputing, p.245-254, July 03-07, 1995, Barcelona, Spain
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	Todd M. Austin , Gurindar S. Sohi, Zero-cycle loads: microarchitecture support for reducing load latency, Proceedings of the 28th annual international symposium on Microarchitecture, p.82-92, November 29-December 01, 1995, Ann Arbor, Michigan, United States
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	Nathalie Drach , Jean-Luc Béchennec , Olivier Temam, Increasing hardware data prefetching performance using the second-level cache, Journal of Systems Architecture: the EUROMICRO Journal, v.48 n.4-5, p.137-149, December 2002
	Onur Mutlu , Hyesoon Kim , David N. Armstrong , Yale N. Patt, Using the first-level caches as filters to reduce the pollution caused by speculative memory references, International Journal of Parallel Programming, v.33 n.5, p.529-559, October 2005
	James Dundas , Trevor Mudge, Improving data cache performance by pre-executing instructions under a cache miss, Proceedings of the 11th international conference on Supercomputing, p.68-75, July 07-11, 1997, Vienna, Austria
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	Andreas Moshovos , Gurindar S. Sohi, Speculative Memory Cloaking and Bypassing, International Journal of Parallel Programming, v.27 n.6, p.427-456, 1999
	Zhong Wang , Edwin Hsing-Mean Sha , Yuke Wang, Partitioning and scheduling DSP applications with maximal memory access hiding, EURASIP Journal on Applied Signal Processing, v.2002 n.1, p.926-935, January 2002
	Han Chen , Kai Li , Bin Wei, Memory Performance Optimizations For Real-Time Software HDTV Decoding, Journal of VLSI Signal Processing Systems, v.41 n.2, p.193-207, September 2005
	Sorin Iacobovici , Lawrence Spracklen , Sudarshan Kadambi , Yuan Chou , Santosh G. Abraham, Effective stream-based and execution-based data prefetching, Proceedings of the 18th annual international conference on Supercomputing, June 26-July 01, 2004, Malo, France
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