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Postplacement rewiring by exhaustive search for functional symmetries
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ACM Transactions on Design Automation of Electronic Systems (TODAES) archive
Volume 12 ,  Issue 3  (August 2007) table of contents
Article No. 32  
Year of Publication: 2007
ISSN:1084-4309
Authors
Kai-Hui Chang  University of Michigan, Ann Arbor, MI
Igor L. Markov  University of Michigan, Ann Arbor, MI
Valeria Bertacco  University of Michigan, Ann Arbor, MI
Publisher
ACM  New York, NY, USA
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ABSTRACT

We propose two new algorithms for rewiring: a postplacement optimization that reconnects pins of a given netlist without changing the logic function and gate locations. In the first algorithm, we extract small subcircuits consisting of several gates from the design and reconnect pins according to the symmetries of the subcircuits. To enhance the power of symmetry detection, we also propose a graph-based symmetry detector that can identify permutational and phase-shift symmetries on multiple input and output wires, as well as hybrid symmetries, creating abundant opportunities for rewiring. Our second algorithm, called long-range rewiring, is based on reconnecting equivalent pins and can augment the first approach for further optimization. We apply our techniques for wirelength optimization and observe that they provide wirelength reduction comparable to that achieved by detailed placement.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Aloul, F. A., Ramani, A., Markov, I. L., and Sakallah, K. A. 2003. Solving difficult instances of Boolean satisfiability in the presence of symmetry. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 22, 9, 1117--1137.
 
3
4
 
5
 
6
Chai, D. and Kuehlmann, A. 2005. Building a better Boolean matcher and symmetry detector. In Proceedings of the IWLS. 391--398.
 
7
Chai, D. and Kuehlmann, A. 2006. A compositional approach to symmetry detection in circuits. In Proceedings of the IWLS. 228--234.
 
8
Chang, C.-W. J., Hsiao, M.-F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C.-K., and Chen, S.-J. 2004. Fast postplacement optimization using functional symmetries. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 23, 1, 102--118.
 
9
 
10
 
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Chang, K.-H., Markov, I. L., and Bertacco, V. 2006. Keeping physical synthesis safe and sound. Tech. rep. CSE-TR-522-06, University of Michigan.
 
12
Chang, S.-C., Cheng, K.-T., Woo, N. S., and Marek-Sadowska, M. 1997. Postlayout logic restructuring using alternative wires. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 16, 6, 587--596.
 
13
 
14
Cong, J. and Long, W. 2001. Theory and algorithm for SPFD-based global rewiring. In Proceedings of the IWLS. 150--155.
15
 
16
Eén, N. and Sörensson, N. 2003. An extensible SAT-solver. In Proceedings of the SAT. 502--518.
 
17
GSRCBookshelf. 2007. http://vlsicad.eecs.umich.edu/BK.
18
 
19
IWLSBenchmarks. 2005. http://iwls.org/iwls2005/benchmarks.html.
20
 
21
 
22
Lu, F., Wang, L.-C., Cheng, K.-T. T., Moondanos, J., and Hanna, Z. 2004. A signal correlation guided circuit-SAT solver. J. UCS 10, 12, 1629--1654.
 
23
Mishchenko, A. 2003. Fast computation of symmetries in Boolean functions. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 22, 11, 1588--1593.
 
24
OpenCores. 2007. http://www.opencores.org/.
 
25
 
26
Pomeranz, I. and Reddy, S. M. 1994. On determining symmetries in inputs of logic circuits. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. 13, 11, 1428--1434.
 
27
Saucy. 2007. http://vlsicad.eecs.umich.edu/bk/saucy/.
 
28
 
29
Wllace, D. E. 2001. Recognizing input equivalence in digital logic. In Proceedings of the IWLS. 207--212.
 
30
 
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Collaborative Colleagues:
Kai-Hui Chang: colleagues
Igor L. Markov: colleagues
Valeria Bertacco: colleagues