Executing loops on a fine-grained MIMD architecture

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Executing loops on a fine-grained MIMD architecture

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International Symposium on Microarchitecture archive
Proceedings of the 24th annual international symposium on Microarchitecture table of contents

Albuquerque, New Mexico, Puerto Rico

Pages: 199 - 205

Year of Publication: 1991

ISBN:0-89791-460-0

Authors

Sunah Lee	Department of Computer Science, University of Pittsburgh, Pittsburgh, PA
Rajiv Gupta	Department of Computer Science, University of Pittsburgh, Pittsburgh, PA

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 4, Citation Count: 2

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. Aiken , A. Nicolau, A Development Environment for Horizontal Microcode, IEEE Transactions on Software Engineering, v.14 n.5, p.584-594, May 1988 [doi>10.1109/32.6136]
	2	A. Aiken , A. Nicolau, Optimal loop parallelization, Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, p.308-317, June 20-24, 1988, Atlanta, Georgia, United States
	3	Robert P. Colwell , Robert P. Nix , John J. O'Donnell , David B. Papworth , Paul K. Rodman, A VLIW architecture for a trace Scheduling Compiler, IEEE Transactions on Computers, v.37 n.8, p.967-979, August 1988 [doi>10.1109/12.2247]
	4	J.A. Fisher, "Trace Scheduling: A Technique for Global Microcode Compaction," IEEE Trans. on Computers, vol. 7, no. C-30, pp. 478-490, July, 1981.
	5	R. Gupta and M.L. Sofia, "Compilation Techniques for a Reconfigurable LIW Architecture," The Journal of Supercomputing, vol. 3, pp. 271-304, 1989.
	6	Rajiv Gupta, The fuzzy barrier: a mechanism for high speed synchronization of processors, Proceedings of the third international conference on Architectural support for programming languages and operating systems, p.54-63, April 03-06, 1989, Boston, Massachusetts, United States
	7	R. Gupta, Employing register channels for the exploitation of instruction level parallelism, Proceedings of the second ACM SIGPLAN symposium on Principles & practice of parallel programming, p.118-127, March 14-16, 1990, Seattle, Washington, United States
	8	Rajiv Gupta , Mary Lou Soffa, Region Scheduling: An Approach for Detecting and Redistributing Parallelism, IEEE Transactions on Software Engineering, v.16 n.4, p.421-431, April 1990 [doi>10.1109/32.54294]
	9	Rajiv Gupta, A fine-grained MIMD architecture based upon register channels, Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture, p.28-37, November 27-29, 1990, Orlando, Florida, United States
	10	John L. Hennessy , Thomas Gross, Postpass Code Optimization of Pipeline Constraints, ACM Transactions on Programming Languages and Systems (TOPLAS), v.5 n.3, p.422-448, July 1983 [doi>10.1145/2166.357217]
	11	D. J. Kuck , R. H. Kuhn , D. A. Padua , B. Leasure , M. Wolfe, Dependence graphs and compiler optimizations, Proceedings of the 8th ACM SIGPLAN-SIGACT symposium on Principles of programming languages, p.207-218, January 26-28, 1981, Williamsburg, Virginia [doi>10.1145/567532.567555]
	12	M. Lam, Software pipelining: an effective scheduling technique for VLIW machines, Proceedings of the ACM SIGPLAN 1988 conference on Programming Language design and Implementation, p.318-328, June 20-24, 1988, Atlanta, Georgia, United States

CITED BY 2

	Kei Hiraki , Junji Tamatsukuri , Takashi Matsumoto, Speculative execution model with duplication, Proceedings of the 12th international conference on Supercomputing, p.321-328, July 1998, Melbourne, Australia
	Bogong Su , Wei Zhao , Zhizhong Tang , Stanley Habib, A VLIW architecture for optimal execution of branch-intensive loops, ACM SIGMICRO Newsletter, v.23 n.1-2, p.119-124, Dec. 1992