| DISC: dynamic instruction stream computer |
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International Symposium on Microarchitecture
archive
Proceedings of the 24th annual international symposium on Microarchitecture
table of contents
Albuquerque, New Mexico, Puerto Rico
Pages: 163 - 171
Year of Publication: 1991
ISBN:0-89791-460-0
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Authors
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Mario Daniel Nemirovsky
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Apple Computer Corporation
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Forrest Brewer
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Electrical and Computer Engineering Department, University of California, Santa Barbara
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Roger C. Wood
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Electrical and Computer Engineering Department, University of California, Santa Barbara
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| Bibliometrics |
Downloads (6 Weeks): 1, Downloads (12 Months): 17, Citation Count: 4
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REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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CPU32, Reference Manual (Rev. 0.8), Motorola 1989
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Thornton J.E., "Parallel Operation in the Control Data 6600," Proceedings-Spring Joint Computer Conference, 1964
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Flynn M.J., Podvin A., and Shimizuk K., "A Multiple Instruction Stream processor with shared resources," Parallel Processor System, C. Hobbs, Washington D.C., Spartan, 1970
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Flynn M.J., "Some Computer Organizations and Their Effectiveness," Transactions on Computers, Vol. C-21, No 9 Sept. 1972
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Kaminsky, W.J. and Davidson E.S., "Developing a Multiple-Instruction-Stream Single-Chip Processor," IEEE Computer Magazine, Dec. 1979
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Smith B.J., "A Pipelined, Shared Resource MIMD Computer," Proc. of the 1978 International Conference on Parallel Processing, 1978
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R. H. Halstead, Jr. , T. Fujita, MASA: a multithreaded processor architecture for parallel symbolic computing, Proceedings of the 15th Annual International Symposium on Computer architecture, p.443-451, May 30-June 02, 1988, Honolulu, Hawaii, United States
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Anant Agarwal , Beng-Hong Lim , David Kranz , John Kubiatowicz, APRIL: a processor architecture for multiprocessing, Proceedings of the 17th annual international symposium on Computer Architecture, p.104-114, May 28-31, 1990, Seattle, Washington, United States
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Patterson D. and Sequin C., "A VLSI RiSC", IEEE Computer Magazine, Sept. 1982
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Alexander G., Wortman D., "Static and Dynamic characteristics of XPL programs," iEEE Computer Magazine, Nov. 1975
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Sites, R.L.,"How to use 1000 registers," Proe. Caltech Conference on VLSI, Jan. t979
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Wyes H.W. and Plessmann K.W., "OMEGA- A RISC Architecture for Real-Time Applications," IFAC 10th Triennial World Congress, Munich, FRG, 1987
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Halbert D. and Kessler P., "Windows of Overlapping Register Frames," CS292R-course final report, UC Berkeley, June 1980
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CITED BY 4
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Ali El-Haj-Mahmoud , Ahmed S. AL-Zawawi , Aravindh Anantaraman , Eric Rotenberg, Virtual multiprocessor: an analyzable, high-performance architecture for real-time computing, Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, September 24-27, 2005, San Francisco, California, USA
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Arun Kejariwal , Alexander V. Veidenbaum , Alexandru Nicolau , Milind Girkar , Xinmin Tian , Hideki Saito, On the exploitation of loop-level parallelism in embedded applications, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.2, p.1-34, January 2009
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