Viewing instruction set design as an optimization problem

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Viewing instruction set design as an optimization problem

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International Symposium on Microarchitecture archive
Proceedings of the 24th annual international symposium on Microarchitecture table of contents

Albuquerque, New Mexico, Puerto Rico

Pages: 153 - 162

Year of Publication: 1991

ISBN:0-89791-460-0

Authors

Bruce K. Holmer	Computer Science Division, University of California, Berkeley, Berkeley, CA and Department of EECS, Northwestern University, 2145 Sheridan Road, Evanston, IL
Alvin M. Despain	Department of Electrical Engineering Systems, University of Southern California, Los Angeles, CA

Sponsors

IEEE-CS : Computer Society
SIGMICRO: ACM Special Interest Group on Microarchitectural Research and Processing

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 24, Citation Count: 4

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	A. M. Abd-Alla and D. C. Karlgaard. Heuristic synthesis of microprogrammed computer architecture. IEEE Transactions on Computers, C- 23(8):802-807, Aug. 1974.
	2	J. P. Bennett. Automated design of an instruction set for BCPL. Technical Report 93, University of Cambridge, Computer Laboratory, 1986.
	3	J. P. Bennett. A Methodology for Automated Design of Computer Instruction Sets. PhD thesis, University of Cambridge, Computer Laboratory, 1988. Also available as Technical Report 129.
	4	Pradip Bose , Edward S. Davidson, Design of instruction set architectures for support of high-level languages, Proceedings of the 11th annual international symposium on Computer architecture, p.198-206, January 1984
	5	W. R. Bush, G. Cheng, P. McGeer, and A. M. Despain. An advanced silicon compiler in Prolog. In Proceedings of ICCAD, 1987.
	6	David Gifford , Alfred Spector, Case study: IBM's system/360-370 architecture, Communications of the ACM, v.30 n.4, p.291-307, April 1987 [doi>10.1145/32232.32233]
	7	Frederick Marion Haney, Using a computer to design computer instruction sets, 1968
	8	F. M. Haney. ISDS--a program that designs computer instruction sets. In Fall Joint Computer Conference, pages 575-580, 1969.
	9	J. Hennessy, N. Jouppi, S. Przybylski, C. Rowen, and T. Gross. Design of a high performance VLSI processor. In Third Caltech Conference on VLSI, page 33, 1983.
	10	Walter Hollingsworth , Howard Sachs , Alan J Smith, The Fairchild CLIPPER: Instruction Set Architecture and Processor, University of California at Berkeley, Berkeley, CA, 1987
	11	B. K. Holmer and A. M. Despain. Optimal instruction sets for Prolog structure creation. Technical Report ACAL 91-4, University of Southern California, Advanced Computer Architecture Research Laboratory, 1991.
	12	Bruce K. Holmer , Barton Sano , Michael Carlton , Peter Van Roy , Ralph Haygood , William R. Bush , Alvin M. Despain , Joan M. Pendleton , Tep Dobry, Fast Prolog with an extended general purpose architecture, Proceedings of the 17th annual international symposium on Computer Architecture, p.282-291, May 28-31, 1990, Seattle, Washington, United States
	13	Gerry Kane, MIPS RISC architecture, Prentice-Hall, Inc., Upper Saddle River, NJ, 1988
	14	P. M. Kogge. The Architecture of Pipelined Computers. McGraw-Hill Book Company, 1981.
	15	S. H. Lavington, The Manchester Mark I and atlas: a historical perspective, Communications of the ACM, v.21 n.1, p.4-12, Jan. 1978 [doi>10.1145/359327.359331]
	16	P. S. Liu and F. J. Mowle. Techniques of program execution with a writable control memory. IEEE Transactions on Compulers, C-27(9):816- 827, Sept. 1978.
	17	Åmund Lunde, Empirical evaluation of some features of instruction set processor architectures, Communications of the ACM, v.20 n.3, p.143-153, March 1977 [doi>10.1145/359436.359442]
	18	J. M. Mulder , R. J. Portier , A. Srivastava , R. in't Velt, An architecture framework for application-specific and scalable architectures, Proceedings of the 16th annual international symposium on Computer architecture, p.362-369, April 1989, Jerusalem, Israel
	19	D. A. Patterson and C. H. Sequin. A VLSI RISC. Computer, 15(9):8-18, Sept. 1982.
	20	J. Pendleton, S. Kong, E. Brown, F. Dunlap, C. Marino, D. Ungar, D. Patterson, and D. Hodges. A 32-bit microprocessor for SmalItalk. IEEE Journal of Solid State Circuits, SC-21(5):741-749, Oct. 1986.
	21	J. M. Pendleton. Private communication about the design of a new SPARC implementation, 1990.
	22	T. G. Rauscher and A. K. Agrawala. Dynamic problem-oriented redefinition of computer architecture via microprogramming. IEEE Transactions on Computers, C-27(11):1006-1014, Nov. 1978.
	23	D.W. Runner and E. H. Warshawsky. Synthesizing Ada's ideal machine mate. VLSI Systems Dcszgn, pages 30-39, Oct. 1988.
	24	Richard E. Sweet , James G. Sandman, Jr., Empirical analysis of the mesa instruction set, Proceedings of the first international symposium on Architectural support for programming languages and operating systems, p.158-166, March 01-03, 1982, Palo Alto, California, United States

CITED BY 4

	Ricardo E. Gonzalez, Xtensa: A Configurable and Extensible Processor, IEEE Micro, v.20 n.2, p.60-70, March 2000
	Joseph A. Fisher , Paolo Faraboschi , Giuseppe Desoli, Custom-fit processors: letting applications define architectures, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.324-335, December 02-04, 1996, Paris, France
	Rahul Razdan , Michael D. Smith, A high-performance microarchitecture with hardware-programmable functional units, Proceedings of the 27th annual international symposium on Microarchitecture, p.172-180, November 30-December 02, 1994, San Jose, California, United States
	Bruce R. Childers , Jack W. Davidson, Custom Wide Counterflow Pipelines for High-Performance Embedded Applications, IEEE Transactions on Computers, v.53 n.2, p.141-158, February 2004

INDEX TERMS

Primary Classification:
C. Computer Systems Organization
C.0 GENERAL
Subjects: Instruction set design (e.g., RISC, CISC, VLIW)

Additional Classification:
B. Hardware
B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
B.1.4 Microprogram Design Aids
Subjects: Optimization

D. Software
D.3 PROGRAMMING LANGUAGES
D.3.4 Processors
Subjects: Optimization

General Terms:
Performance, Theory

Collaborative Colleagues:

Bruce K. Holmer: colleagues

Alvin M. Despain: colleagues

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